Quantum well stacks for quantum dot devices

Patent metadata

Field	Value
Publication number	US-11114530-B2
Application number	US-201716648442-A
Country	US
Kind code	B2
Filing date	Dec 17, 2017
Priority date	Dec 17, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; and
a gate above the quantum well stack,
wherein the isotopically purified material includes silicon and germanium.

2. The quantum dot device of claim 1 , wherein the silicon includes 29Si in an amount less than 4 atomic-percent.

3. The quantum dot device of claim 1 , wherein the germanium includes 73Ge in an amount less than 7 atomic-percent.

4. The quantum dot device of claim 1 , wherein the isotopically purified material is a first isotopically purified material, the quantum well stack further includes a buffer layer, the buffer layer includes a second isotopically purified material, the gate includes a gate dielectric, and the quantum well layer is between the buffer layer and the gate dielectric.

5. The quantum dot device of claim 4 , wherein the second isotopically purified material includes zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

6. The quantum dot device of claim 4 , wherein a thickness of the buffer layer is greater than 25 nanometers.

7. The quantum dot device of claim 4 , wherein the quantum well stack further includes a barrier layer, the barrier layer includes a third isotopically purified material, and the barrier layer is between the quantum well layer and the gate dielectric.

8. The quantum dot device of claim 4 , further comprising:
a barrier layer, wherein the buffer layer is between the quantum well layer and the barrier layer.

9. The quantum dot device of claim 1 , wherein the gate includes a gate dielectric, the isotopically purified material is a first isotopically purified material, and the gate dielectric includes a second isotopically purified material.

10. The quantum dot device of claim 9 , wherein the second isotopically purified material includes silicon.

11. The quantum dot device of claim 9 , wherein the second isotopically purified material includes hafnium.

12. The quantum dot device of claim 11 , wherein the hafnium of the second isotopically purified material includes 177Hf in an amount less than 18 atomic-percent.

13. The quantum dot device of claim 9 , wherein the second isotopically purified material includes zirconium, titanium, strontium, or yttrium.

14. The quantum dot device of claim 9 , wherein the gate dielectric is on the quantum well layer.

15. The quantum dot device according to claim 1 , wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device,
the quantum processing device includes the quantum well stack and the gate, and
the non-quantum processing device is coupled to the quantum processing device and configured to control a voltage applied to the gate.

16. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum well stack including a quantum well layer and a buffer layer, the quantum well layer includes first isotopically purified material, the buffer layer includes a second isotopically purified material, and the quantum processing device further includes at least one gate above the quantum well stack to control quantum dot formation in the quantum well stack; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the at least one gate,
wherein:
the gate at least one gate includes a gate dielectric,
the quantum well layer is between the buffer layer and the gate dielectric,
the quantum computing device further includes a barrier layer, and
the buffer layer is between the quantum well layer and the barrier layer.

17. The quantum computing device of claim 16 , further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

18. A quantum dot device, comprising:
a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; and
a gate above the quantum well stack;
wherein the isotopically purified material includes at least one of zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, and carbon.

19. The quantum dot device according to claim 18 , wherein:
the gate includes a gate dielectric and a gate metal,
the gate dielectric above the quantum well stack, and
the gate dielectric is between the quantum well layer and the gate metal.

20. The quantum dot device according to claim 18 , wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device,
the quantum processing device includes the quantum well stack and the gate, and
the non-quantum processing device is coupled to the quantum processing device and configured to control a voltage applied to the gate.

Assignees

• Intel Corp

Inventors

• Thomas Nicole K
• Clarke James S
• Torres Jessica M
• Pillarisetty Ravi
• Singh Kanwaljit
• Amin Payam
• George Hubert C
• Roberts Jeanette M
• Caudillo Roman
• Michalak David J
• Yoscovits Zachary R
• Lampert Lester

Classifications

• H10D48/3835

  Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D48/385

  Devices using spin-polarised carriers · CPC title