SOI semiconductor structure and method for manufacturing an SOI semiconductor structure

Patent metadata

Field	Value
Publication number	US-11114501-B2
Application number	US-201916691082-A
Country	US
Kind code	B2
Filing date	Nov 21, 2019
Priority date	Nov 21, 2018
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

First claim

What is claimed is:

1. An SOI semiconductor structure comprising:
a second semiconductor wafer formed as a substrate layer on a back side and a semiconductor layer formed on a front side of a first semiconductor wafer;
an insulating layer disposed between the substrate layer and the semiconductor layer;
a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body and having an integrated circuit formed in the semiconductor layer, he semiconductor body having a second conductivity type and extends from a buried lower surface towards the front side;
at least three first metallic terminal contacts spaced a distance apart, being formed on the front side;
at least three second terminal contacts spaced a distance apart, being formed on the lower surface, each of the at least three second terminal contacts comprising a highly doped polysilicon of a second conductivity type or a metal;
wherein, each of the at least three first terminal contacts and each of the at least three second terminal contacts being formed on a highly doped semiconductor contact region of a second conductivity type,
wherein at least a portion of the at least three first terminal contacts being formed on the highly doped connecting regions being offset with respect to at least a portion of the at least three second terminal contacts formed on the highly doped connecting region in a projection substantially perpendicular to the front side,
wherein the at least three first terminal contacts and the at least three second terminal contacts each have a multiple rotational symmetry with respect to an axis of symmetry viewed perpendicularly on the front side and on the lower surface of the semiconductor body, and
wherein the lower surface of the semiconductor body being formed on the insulating layer.

2. The SOI semiconductor structure according to claim 1 , wherein the semiconductor body is electrically insulated from the remaining semiconductor layer via a circumferential trench structure.

3. The SOI semiconductor structure according to claim 1 , wherein the semiconductor body has a thickness between 2 μm and 30 μm in the sensor region.

4. The SOI semiconductor structure according to claim 1 , wherein a ratio between a thickness and a length of the semiconductor body in the sensor region is in a range between 0.6 and 1.4 or in a range between 0.8 and 1.2.

5. The SOI semiconductor structure according to claim 1 , wherein the second terminal contacts are electrically connected from the front side of the SOI semiconductor structure.

6. The SOI semiconductor structure according to claim 1 , wherein the second terminal contacts are electrically connected from the back side of the SOI semiconductor structure.

7. The SOI semiconductor structure according to claim 1 , wherein the semiconductor layer has a lower thickness outside the sensor region than within the sensor region, the thickness of the semiconductor layer outside the sensor region being in a range between 0.1 μm and 10 μm or in a range between 0.5 μm and 2 μm.

8. The SOI semiconductor structure according to claim 1 , wherein the integrated circuit is in an electrical operative connection with the Hall sensor structure.

9. The SOI semiconductor structure according to claim 1 , wherein the semiconductor layer, outside of the Hall sensor structure, has at least one region of a first conductivity type.

10. The SOI semiconductor structure according to claim 1 , wherein a first conductivity type is p and the second conductivity type is n or vice versa.

Assignees

• Tdk Micronas Gmbh

Inventors

• Sander Christian
• Cornils Martin

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10N59/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) · CPC title

• H01L21/76251

  Electricity · mapped topic