Array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11114477-B2
Application number	US-201816094315-A
Country	US
Kind code	B2
Filing date	Aug 23, 2018
Priority date	Jul 4, 2018
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

In a method for manufacturing an array substrate, a first photoresist pattern is formed on a buffer layer of a non-display region and the buffer layer uncovered by the first photoresist pattern is removed to form a first via hole in the non-display region. A second via hole is formed on the basis of the first via hole. The second via hole is connected to the first via hole. By forming the first via hole in the non-display region and forming the second via hole on the basis of the first via hole, completeness of film layers is ensured and product yield is improved.

First claim

The invention claimed is:

1. A method for manufacturing an array substrate, comprising:
forming a buffer layer on a substrate, the substrate comprising a display region and a non-display region;
forming a first photoresist pattern on the buffer layer of the non-display region and removing a part of the buffer layer to form a first via hole in the non-display region;
forming an insulating layer on the buffer layer of the non-display region and the first via hole; and
forming a second photoresist pattern on the insulating layer of the non-display region and removing a part of the insulating layer to form a second via hole in the non-display region, the second photoresist pattern corresponding to the first via hole and the second via hole connected to the first via hole,
wherein the insulating layer at least partially covers the first via hole and a cross-sectional area of the second via hole is less than or equal to a cross-sectional area of the first via hole, and
wherein a thickness of the first via hole is between 0.7 micrometer and 0.9 micrometer and a thickness of the second via hole is between 0.6 micrometer and 0.8 micrometer.

2. The method according to claim 1 , wherein after the step of removing the part of the insulating layer to form the second via hole in the non-display region, the method further comprises:
filling an organic material into the first via hole and the second via hole to form an organic insulating layer in the first via hole and the second via hole, wherein the organic insulating layer contacts the substrate via the first via hole and the second via hole; and
sequentially forming a metal layer, an organic flat layer, and a pixel defining layer on the organic insulating layer.

3. The method according to claim 2 , wherein the step of forming the first photoresist pattern on the buffer layer of the non-display region and removing the part of the buffer layer to form the first via hole in the non-display region comprises:
forming a first photoresist layer on the buffer layer of the non-display region and processing the first photoresist layer by exposure and development to form the first photoresist pattern on the buffer layer of the non-display region; and
etching the buffer layer uncovered by the first photoresist pattern to form the first via hole in the non-display region.

4. The method according to claim 2 , wherein the step of forming the second photoresist pattern on the insulating layer of the non-display region and removing the part of the insulating layer to form the second via hole in the non-display region comprises:
forming a second photoresist layer on the insulating layer of the non-display region and processing the second photoresist layer by exposure and development to form the second photoresist pattern on the insulating layer of the non-display region; and
etching the insulating layer uncovered by the second photoresist pattern to form the second via hole in the non-display region.

5. The method according to claim 4 , further comprising:
sequentially forming a thin-film transistor pattern and the insulating layer on the buffer layer of the display region;
forming the second photoresist layer on the insulating layer and processing the second photoresist layer by the exposure and the development to form a third photoresist pattern and a fourth photoresist pattern on the insulating layer of the display region; and
removing the insulating layer uncovered by the third photoresist pattern and the fourth photoresist pattern to form a third via hole and a fourth via hole in the display region,
wherein the third via hole and the fourth via hole run through the thin-film transistor pattern and the insulating layer and are disposed at two sides of the thin-film transistor pattern,
wherein a source electrode is formed in the third via hole, a drain electrode is formed in the fourth via hole, and the source electrode and the drain electrode at least covers a part of the insulating layer, and
wherein an organic flat layer, an anode, a pixel defining layer, and a spacer are sequentially formed on the source electrode and the drain electrode.

6. The method according to claim 1 , wherein the insulating layer is made of polyimide resin or poly(methyl methacrylate).

7. The method according to claim 1 , wherein a flexible material is filled into the first via hole and the second via hole to increase flexibility of the array substrate.

8. A method for manufacturing an array substrate, comprising:
forming a buffer layer on a substrate, the substrate comprising a display region and a non-display region;
forming a first photoresist pattern on the buffer layer of the non-display region and removing a part of the buffer layer to form a first via hole in the non-display region;
forming an insulating layer on the buffer layer of the non-display region and the first via hole; and
forming a second photoresist pattern on the insulating layer of the non-display region and removing a part of the insulating layer to form a second via hole in the non-display region, wherein the second photoresist pattern corresponds to the first via hole and the second via hole is connected to the first via hole.

9. The method according to claim 8 , wherein after the step of removing the part of the insulating layer to form the second via hole in the non-display region, the method further comprises:
filling an organic material into the first via hole and the second via hole to form an organic insulating layer in the first via hole and the second via hole, wherein the organic insulating layer contacts the substrate via the first via hole and the second via hole; and
sequentially forming a metal layer, an organic flat layer, and a pixel defining layer on the organic insulating layer.

10. The method according to claim 9 , wherein the step of forming the first photoresist pattern on the buffer layer of the non-display region and removing the part of the buffer layer to form the first via hole in the non-display region comprises:
forming a first photoresist layer on the buffer layer of the non-display region and processing the first photoresist layer by exposure and development to form the first photoresist pattern on the buffer layer of the non-display region; and
etching the buffer layer uncovered by the first photoresist pattern to form the first via hole in the non-display region.

11. The method according to claim 9 , wherein the step of forming the second photoresist pattern on the insulating layer of the non-display region and removing the part of the insulating layer to form the second via hole in the non-display region comprises:
forming a second photoresist layer on the insulating layer of the non-display region and processing the second photoresist layer by exposure and development to form the second photoresist pattern on the insulating layer of the non-display region; and
etching the insulating layer uncovered by the second photoresist pattern to form the second via hole in the non-display region.

12. The method according to claim 11 , further comprising:
sequentially forming a thin-film transistor pattern and the insulating layer on the buffer layer of the display region;
forming the second photoresist layer on the insulating layer and processing the second photoresist layer by the exposure and the development to form a third photoresist pattern and a fourth photoresist pattern on the insulating layer of the display region; and
removing the insulating layer uncovered by the third photoresist pattern and the fourth photoresist pattern to form a third via hole and a fourth via hole in the display region,
wherein the third via hole and the fourt

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Chen Caiqin
• Ming Xing

Classifications

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D30/6731 Primary

  Top-gate only TFTs · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title