Array substrate and fabricating method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-11114469-B2
Application number	US-201916396726-A
Country	US
Kind code	B2
Filing date	Apr 28, 2019
Priority date	Jul 27, 2018
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.

First claim

What is claimed is:

1. A system, comprising:
an array substrate, comprising:
an indium gallium zinc oxide (IGZO) film layer;
a gate layer with a disconnected portion at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line, the first gate line and the second gate line being configured to detect conductorization of indium gallium zinc oxide; and
a gate insulating layer disposed between the IGZO film layer and the gate layer, and provided with at least two through holes thereon, wherein the disconnected portion is between the at least two through holes, the first gate line is connected with the IGZO film layer through at least one through hole, and the second gate line is connected with the IGZO film layer through another at least one through hole such that the IGZO film layer is connected in series with the gate layer.

2. The system according to claim 1 , wherein the IGZO film layer is disposed under the gate insulating layer, and the gate layer is disposed over the gate insulating layer.

3. The system of claim 2 , wherein the array substrate further comprises:
a substrate;
a light shielding layer disposed over the substrate;
a buffer layer disposed over the light shielding layer and the substrate, the IGZO film layer being disposed on the buffer layer;
an interlayer insulating layer disposed over the gate layer and the buffer layer;
a source/drain layer disposed over the interlayer insulating layer;
a passivation layer disposed over the source/drain layer; and
a pixel electrode layer disposed over the passivation layer.

4. The system according to claim 1 , wherein the IGZO film layer is disposed over the gate insulating layer, and the gate layer is disposed under the gate insulating layer.

5. The system according to claim 1 , further comprising: a display panel, wherein the display panel comprises the array substrate.

6. The system according to claim 5 , wherein the IGZO film layer is disposed under the gate insulating layer, and the gate layer is disposed over the gate insulating layer.

7. The system according to claim 6 , wherein the array substrate further comprises:
a substrate;
a light shielding layer disposed over the substrate;
a buffer layer disposed over the light shielding layer and the substrate, the IGZO film layer being disposed on the buffer layer;
an interlayer insulating layer disposed over the gate layer and the buffer layer;
a source/drain layer disposed over the interlayer insulating layer;
a passivation layer disposed over the source/drain layer; and
a pixel electrode layer disposed over the passivation layer.

8. The system according to claim 5 , wherein the IGZO film layer is disposed over the gate insulating layer, and the gate layer is disposed under the gate insulating layer.

9. The system according to claim 5 , further comprising: a display device, wherein the display device comprises the display panel.

10. The system according to claim 9 , wherein the IGZO film layer is disposed under the gate insulating layer, and the gate layer is disposed over the gate insulating layer.

11. The system according to claim 10 , wherein the array substrate further comprises:
a substrate;
a light shielding layer disposed over the substrate;
a buffer layer disposed over the light shielding layer and the substrate, the IGZO film layer being disposed on the buffer layer;
an interlayer insulating layer disposed over the gate layer and the buffer layer;
a source/drain layer disposed over the interlayer insulating layer;
a passivation layer disposed over the source/drain layer; and
a pixel electrode layer disposed over the passivation layer.

12. The system according to claim 9 , wherein the IGZO film layer is disposed over the gate insulating layer, and the gate layer is disposed under the gate insulating layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhou Bin
• Cao Binbin
• Yan Liangchen
• Wang Dongfang
• Zhao Ce
• Ding Luke
• Liu Jun

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title