Memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-11114172-B2
Application number	US-202016930919-A
Country	US
Kind code	B2
Filing date	Jul 16, 2020
Priority date	Feb 5, 2020
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including super blocks, each of the super blocks including a plurality of memory blocks, and a controller configured to control the memory device so that a program operation is performed on a selected memory block within any one of the super blocks based on a request from a host, wherein, when a program fail occurs during the program operation that is performed on the selected memory block of the selected super block, the controller is configured to control the memory device so that a test read operation is performed on remaining memory blocks, besides the selected memory block, of the selected super block.

First claim

What is claimed is:

1. A memory system, comprising:
a memory device including super blocks, each of the super blocks including a plurality of memory blocks; and
a controller configured to control the memory device so that a program operation is performed on a selected memory block within any one of the super blocks based on a request from a host,
wherein, when a program fail occurs during the program operation that is performed on the selected memory block of the selected super block, the controller is configured to control the memory device so that a test read operation is performed on remaining memory blocks, besides the selected memory block, of the selected super block.

2. The memory system according to claim 1 , wherein, when the program fail occurs in the selected memory block, the memory device is configured to select a new memory block in an erased state from among the plurality of memory blocks of the selected super block and perform the program operation on the new memory block.

3. The memory system according to claim 1 , wherein the memory device performs the test read operation on a page within one of the remaining memory blocks of the selected super block, and
wherein the page on which the test read operation is performed is identical to a page in which the program fail has occurred in the selected memory block of the selected super block.

4. The memory system according to claim 1 , wherein the memory device performs the test read operation on all pages of the remaining memory blocks during the test read operation.

5. The memory system according to claim 1 , wherein the controller controls the memory device so that a data shift operation is performed on a memory block in which a fail has occurred as a result of the test read operation.

6. The memory system according to claim 5 , wherein the data shift operation is configured to read valid data that is stored in the memory block in which the fail has occurred and configured to store the valid data in a new memory block, among the remaining memory blocks, in an erased state.

7. The memory system according to claim 6 , wherein the controller manages the super block so that the new memory block is included in the selected super block, which includes the selected memory block in which the fail has occurred.

8. A memory system, comprising:
a memory device including a plurality of memory blocks; and
a controller configured to control the memory device so that a program operation is performed on a first memory block, among the plurality of memory blocks, based on a request from a host,
wherein, when a program fail occurs during the program operation that is performed on the first memory block, the controller is configured to control the memory device so that a test read operation is performed on second memory blocks in a same super block as the first memory block and configured to control the memory device so that a data shift operation is performed on the second memory blocks based on a result of the test read operation.

9. The memory system according to claim 8 , wherein the controller comprises:
a processor configured to manage the super block and to control the memory device so that the test read operation is performed; and
an error correction circuit configured to determine the result of the test read operation.

10. The memory system according to claim 9 , wherein:
the processor controls the memory device so that the data shift operation is performed on third memory blocks, among the second memory blocks, in which a fail has occurred as the result of the test read operation, and
the data shift operation is configured to shift valid data that is stored in the third memory blocks to fourth memory blocks, among the plurality of memory blocks, in an erased state and to store the valid data in the fourth memory blocks.

11. The memory system according to claim 10 , wherein the processor manages the super block so that the fourth memory blocks for which the data shift operation has been completed are included in the same super block as the first memory block and the second memory block.

12. The memory system according to claim 8 , wherein the memory device performs the test read operation on a page within the second memory blocks of the super block, and
wherein the page on which the test read operation is performed is identical to a page in which the program fail has occurred in the first memory block of the super block.

13. The memory system according to claim 8 , wherein the memory device performs the test read operation on all pages of the second memory blocks during the test read operation.

14. A method of operating a memory system, comprising:
performing a program operation on a memory block that is selected from among a plurality of memory blocks;
when a program fail occurs in the selected memory block, performing a test read operation on remaining memory blocks, besides the selected memory block, included in a same super block as the selected memory block; and
performing a data shift operation on memory blocks, among the remaining memory blocks, in which a read fail has occurred as a result of the test read operation.

15. The method according to claim 14 , further comprising:
when the program fail occurs in the selected memory block, determining that the selected memory block is a bad block, selecting a new memory block, among the plurality of memory blocks, in an erased state, and re-performing the program operation on the new memory block.

16. The method according to claim 14 , wherein the test read operation is performed on a page within one of the remaining memory blocks of the super block, and
wherein the page on which the test read operation is performed is identical to a page in which the program fail has occurred in the selected memory block of the super block.

17. The method according to claim 14 , wherein the test read operation is performed on all pages of the remaining memory blocks during the test read operation.

18. The method according to claim 14 , wherein the data shift operation is configured to read valid data that is stored in the memory blocks in which the read fail has occurred and configured to store the valid data in new memory blocks, among the plurality of memory blocks, in an erased state.

19. The method according to claim 18 , wherein the super block is managed such that the new memory blocks in the erased state are included in the super block.

20. The method according to claim 14 , wherein the plurality of memory blocks are managed to be grouped into a plurality of super blocks.

Assignees

• Sk Hynix Inc

Inventors

• Bae Sung Won
• Jung Dong Jae

Classifications

• G11C2029/0409

  Online test · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/38

  Response verification devices · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title