Reference voltage training circuit and semiconductor apparatus including the same

Patent metadata

Field	Value
Publication number	US-11114142-B2
Application number	US-202016862172-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Sep 26, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.

First claim

What is claimed is:

1. A reference voltage training circuit comprising:
a normal buffer configured to generate a first received signal by receiving one of two differential signals based on the other of the two differential signals;
a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing a phase of the second received signal with a phase of the first received signal; and
a reference voltage generation circuit configured to calibrate a level of the reference voltage according to the reference voltage calibration signals.

2. The reference voltage training circuit according to claim 1 , wherein the calibration signal generation circuit comprises:
a replica buffer configured to receive the one of the differential signals according to the reference voltage and generate the second received signal; and
a phase detector configured to generate the reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal.

3. The reference voltage training circuit according to claim 2 , wherein the replica buffer is configured by replicating the normal buffer.

4. The reference voltage training circuit according to claim 2 , wherein when the phase of the second received signal leads the phase of the first received signal, the phase detector changes one of the reference voltage calibration signals to a high level at a rising edge of a second pulse of the second received signal.

5. The reference voltage training circuit according to claim 4 , wherein when the phase of the first received signal leads the phase of the second received signal, the phase detector changes the other of the reference voltage calibration signals to a high level at a rising edge of a second pulse of the first received signal.

6. The reference voltage training circuit according to claim 1 , wherein the reference voltage generation circuit comprises:
a voltage generation circuit configured to generate pre-reference voltages using a supply voltage according to a target voltage, select one of the pre-reference voltages according to a voltage calibration code, and output the selected voltage as the reference voltage; and
a code generation circuit configured to generate the value of the voltage calibration code according to the reference voltage calibration signal.

7. The reference voltage training circuit according to claim 6 , wherein the voltage generation circuit comprises:
an amplifier configured to amplify and output a difference between the target voltage and a feedback voltage;
a driver coupled to a supply voltage terminal;
a divider resistor coupled between the driver and a ground voltage terminal and configured to provide to the amplifier one of the pre-reference voltages applied to nodes as the feedback voltage; and
a multiplexer configured to select and output, as the reference voltage, one of the pre-reference voltages according to the voltage calibration code.

8. The reference voltage training circuit according to claim 1 , wherein the differential signals comprise differential data strobe signals.

9. A semiconductor apparatus comprising:
a differential signal receiving circuit configured to generate reference voltage calibration signals according to differential signals and a reference voltage;
a data receiving circuit configured to receive data transmitted from an external semiconductor apparatus according to the reference voltage; and
a reference voltage generation circuit configured to calibrate a level of the reference voltage according to the reference voltage calibration signals.

10. The semiconductor apparatus according to claim 9 , wherein the differential signals comprise differential data strobe signals.

11. The semiconductor apparatus according to claim 9 , wherein the differential signal receiving circuit:
receives a first of the differential signals as a first received signal based on a second of the differential signals,
receives the first differential signal as a second received signal based on the reference voltage, and
generates the reference voltage calibration signals by comparing a phase of the first received signal to a phase of the second received signal.

12. The semiconductor apparatus according to claim 9 , wherein the differential signal receiving circuit comprises:
a normal buffer configured to receive the first differential signal based on the second differential signal and generate the first received signal;
a replica buffer configured to generate the second received signal by receiving the first differential signal according to the reference voltage; and
a phase detector configured to generate the reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal.

13. The semiconductor apparatus according to claim 12 , wherein the replica buffer is configured by replicating the normal buffer.

14. The semiconductor apparatus according to claim 12 , wherein when the phase of the second received signal leads the phase of the first received signal, the phase detector changes one of the reference voltage calibration signals to a high level at a rising edge of a second pulse of the second received signal.

15. The semiconductor apparatus according to claim 14 , wherein when the phase of the first received signal leads the phase of the second received signal, the phase detector changes the other of the reference voltage calibration signals to a high level at a rising edge of a second pulse of the first received signal.

16. The semiconductor apparatus according to claim 9 , wherein the reference voltage generation circuit comprises:
a voltage generation circuit configured to generate pre-reference voltages using a supply voltage according to a target voltage, select one of the pre-reference voltages according to a voltage calibration code, and output the selected voltage as the reference voltage; and
a code generation circuit configured to generate the voltage calibration code according to the reference voltage calibration signals.

17. The semiconductor apparatus according to claim 16 , wherein the voltage generation circuit comprises:
an amplifier configured to amplify and output a difference between the target voltage and a feedback voltage;
a driver coupled to a supply voltage terminal;
a divider resistor coupled between the driver and a ground voltage terminal and configured to provide the amplifier one of the pre-reference voltages applied to nodes as the feedback voltage; and
a multiplexer configured to select and output, as the reference voltage, one of the pre-reference voltages according to the voltage calibration code.

18. A reference voltage training circuit comprising:
first circuitry configured to generate a first signal by comparing levels of differential signals;
second circuitry configured to generate a second signal by comparing a level of a reference signal with a level of one of the differential signals;
third circuitry configured to generate a calibration code by comparing phases of the first and second signals; and
fourth circuitry configured to move, according to the calibration code, a level of the reference signal toward a mid-level of the differential signals.

19. The reference voltage training circuit according to claim 18 , wherein when the phase of the second signal leads the phase of

Assignees

• Sk Hynix Inc

Inventors

• Kim Hee Jun

Classifications

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C7/1084 Primary

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title