Image processing device, method of controlling image processing device, and display device

US11114001B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11114001-B2
Application numberUS-201916601618-A
CountryUS
Kind codeB2
Filing dateOct 15, 2019
Priority dateOct 16, 2018
Publication dateSep 7, 2021
Grant dateSep 7, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A projector configured to generate a first image and a second image to be displayed by a projection section, the projection section displaying first pixels constituting the first image and second pixels constituting the second image so that the second pixels are shifted with respect to corresponding ones of the first pixels, includes a filter processing circuit configured to execute a filter process of limiting a frequency band of an image signal of an input image with a one-dimensional filter to generate an intermediate image, an image expanding circuit configured to expand the intermediate image to generate a second expanded image, and an image dividing circuit configured to divide some of second expanded pixels constituting the second expanded image into the first image and the second image.

First claim

Opening claim text (preview).

What is claimed is: 1. An image processing device configured to generate a first image and a second image so that first pixels constituting the first image and second pixels constituting the second image are displayed so as to be shifted from each other, the image processing device comprising: a filter processing circuit configured to execute a filter process of limiting a frequency band of an image signal of an input image with a one-dimensional filter to generate an intermediate image; an image expanding circuit configured to expand the intermediate image generated by the filter processing circuit to generate an expanded image; and an image dividing circuit configured to divide some of pixels constituting the expanded image generated by the image expanding circuit into the first image and the second image; wherein the one-dimensional filter includes a first filter configured as a low-pass filter and a second filter configured as a low-pass filter, pixels constituting the input image are arranged in a first direction and a second direction crossing the first direction, and the filter processing circuit comprises a filter processing circuit configured for limiting a frequency band in the first direction of the input image with the first filter, and for limiting a frequency band in the second direction of the input image with the second filter. 2. The image processing device according to claim 1 , wherein the first filter and the second filter are configured so that a sum of a maximum frequency in the first direction of the intermediate image and a maximum frequency in the second direction becomes one of equal to and lower than a predetermined frequency. 3. The image processing device according to claim 1 , wherein the image expanding circuit comprises an image expanding circuit configured for performing the expansion so that a sum of a number of pixels of the first image and a number of pixels of the second image becomes one of equal to and larger than a number of pixels constituting the input image. 4. The image processing device according to claim 1 , wherein the image dividing circuit comprises an image dividing circuit configured for dividing pixels arranged in a zigzag manner out of the pixels constituting the expanded image into the first image and the second image. 5. The image processing device according to claim 1 , wherein the pixels constituting the expanded image are arranged in a first direction and a second direction crossing the first direction, and in the expanded image, the second pixels represent pixels located at a distance of one pixel in the first direction with respect to the first pixels, and located at a distance of one pixel in the second direction with respect to the first pixels. 6. A method of controlling an image processing device configured to generate a first image and a second image so that first pixels constituting the first image and second pixels constituting the second image are displayed so as to be shifted from each other, the method comprising: executing a filter process of limiting a frequency band of an image signal of an input image with a one-dimensional filter to generate an intermediate image; expanding the intermediate image to generate an expanded image; and dividing some of pixels constituting the expanded image into the first image and the second image; wherein the one-dimensional filter includes a first filter configured as a low-pass filter and a second filter configured as a low-pass filter, pixels constituting the input image are arranged in a first direction and a second direction crossing the first direction, and a frequency band in the first direction of the input image is limited by the first filter, and a frequency band in the second direction of the input image is limited b the second filter. 7. The method of controlling the image processing device according to claim 6 , wherein the first filter and the second filter are configured so that a sum of a maximum frequency in the first direction of the intermediate image and a maximum frequency in the second direction becomes one of equal to and lower than a predetermined frequency. 8. The method of controlling the image processing device according to claim 6 , wherein the expansion is performed so that a sum of a number of pixels of the first image and a number of pixels of the second image becomes one of equal to and larger than a number of pixels constituting the input image. 9. The method of controlling the image processing device according to claim 6 , wherein pixels arranged in a zigzag manner out of the pixels constituting the expanded image are divided into the first image and the second image. 10. The method of controlling the image processing device according to claim 6 , wherein the pixels constituting the expanded image are arranged in a first direction and a second direction crossing the first direction, and in the expanded image, the second pixels represent pixels located at a distance of one pixel in the first direction with respect to the first pixels, and located at a distance of one pixel in the second direction with respect to the first pixels. 11. A display device comprising: a display section configured to display first pixels constituting a first image and second pixels constituting a second image so that the second pixels are shifted with respect to corresponding ones of the first pixels; and an image processing section configured to generate the first image and the second image, wherein the image processing section includes a filter processing circuit configured to execute a filter process of limiting a frequency band of an image signal of an input image with a one-dimensional filter to generate an intermediate image, an image expanding circuit configured to expand the intermediate image generated by the filter processing circuit to generate an expanded image, and an image dividing circuit configured to divide some of pixels constituting the expanded image generated by the image expanding circuit into the first image and the second image; wherein the one-dimensional filter includes a first filter configured as a low-pass filter and a second filter configured as a low pass filter, pixels constituting the input image are arranged in a first direction and a second direction crossing the first direction, and the filter processing circuit comprises a filter processing circuit configured for limiting a frequency band in the first direction of the input image with the first filter, and for limiting a frequency band in the second direction of the input image with the second filter. 12. The display device according to claim 11 , wherein the first filter and the second filter are configured so that a sum of a maximum frequency in the first direction of the intermediate image and a maximum frequency in the second direction becomes one of equal to and lower than a predetermined frequency. 13. The display device according to claim 11 , wherein the image expanding circuit comprises an image expanding circuit configured for performing the expansion so that a sum of a number of pixels of the first image and a number of pixels of the second image becomes one of equal to and larger than a number of pixels constituting the input image. 14. The display device according to claim 11 , wherein the image dividing circuit comprises an image dividing circuit configured for dividing pixels arranged in a zigzag manner out of the pixels constituting the expanded image into the first image and the second image. 15. The display device according to claim 11 , wherein the

Assignees

Inventors

Classifications

  • Scaling of whole images or parts thereof, e.g. expanding or contracting · CPC title

  • using local operators · CPC title

  • Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

  • Aspects of display data processing · CPC title

  • Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

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What does patent US11114001B2 cover?
A projector configured to generate a first image and a second image to be displayed by a projection section, the projection section displaying first pixels constituting the first image and second pixels constituting the second image so that the second pixels are shifted with respect to corresponding ones of the first pixels, includes a filter processing circuit configured to execute a filter pr…
Who is the assignee on this patent?
Seiko Epson Corp, Seiko Espon Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/007. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).