Tunneling functional safety communications over an enhanced serial peripheral interface

US11113402B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11113402-B2
Application numberUS-201916370566-A
CountryUS
Kind codeB2
Filing dateMar 29, 2019
Priority dateMar 29, 2019
Publication dateSep 7, 2021
Grant dateSep 7, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

First claim

Opening claim text (preview).

We claim: 1. A system comprising: a vehicle subsystem; a system on chip (SoC) coupled to the vehicle subsystem, the SoC including a root of trust; an embedded controller to conduct functional safety operations and non-functional safety operations; and an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust. 2. The system of claim 1 , wherein the communications are to include data collection traffic. 3. The system of claim 1 , wherein the root of trust includes a security unit. 4. The system of claim 1 , wherein the root of trust includes a power management unit. 5. The system of claim 1 , wherein the root of trust includes an internal safety unit. 6. The system of claim 1 , wherein the embedded controller is to power on before the SoC. 7. An apparatus comprising: a system on chip (SoC) including a root of trust; an embedded controller to conduct functional safety operations in compliance with one or more safety requirements and conduct non-functional safety operations; and an interface coupled to the SoC and the embedded controller, wherein the interface is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust, wherein the interface is an enhanced serial peripheral interface (eSPI). 8. The apparatus of claim 7 , wherein the communications are to include data collection traffic. 9. The apparatus of claim 7 , wherein the root of trust includes one or more of a security unit or a power management unit. 10. The apparatus of claim 7 , wherein the root of trust includes an internal safety unit. 11. The apparatus of claim 7 , wherein the embedded controller is to power on before the SoC. 12. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by an embedded controller, cause the embedded controller to: conduct functional safety operations with respect to a system on chip (SoC) including a root of trust; conduct non-functional safety operations with respect to the SoC; and tunnel communications associated with the functional safety operations to the root of trust via an enhanced serial peripheral interface (eSPI). 13. The at least one non-transitory computer readable storage medium of claim 12 , wherein the communications are to include data collection traffic. 14. The at least one non-transitory computer readable storage medium of claim 12 , wherein the communications are to be tunneled to a security unit in the root of trust. 15. The at least one non-transitory computer readable storage medium of claim 12 , wherein the communications are to be tunneled to a power management unit in the root of trust. 16. The at least one non-transitory computer readable storage medium of claim 12 , wherein the communications are to be tunneled to an internal safety unit in the root of trust. 17. The at least one non-transitory computer readable storage medium of claim 12 , wherein the embedded controller is to power on before the SoC. 18. A method comprising: conducting, by an embedded controller, functional safety operations with respect to a system on chip (SoC) including a root of trust; conducting, by the embedded controller, non-functional safety operations with respect to the SoC; and tunneling communications associated with the functional safety operations from the embedded controller to the root of trust via an enhanced serial peripheral interface (eSPI). 19. The method of claim 18 , wherein the communications include data collection traffic. 20. The method of claim 18 , wherein the communications are tunneled to a security unit in the root of trust. 21. The method of claim 18 , wherein the communications are tunneled to a power management unit in the root of trust. 22. The method of claim 18 , wherein the communications are tunneled to an internal safety unit in the root of trust. 23. The method of claim 18 , wherein the embedded controller powers on before the SoC.

Assignees

Inventors

Classifications

  • Safety, monitoring · CPC title

  • Safety, monitoring (G05B19/0423 takes precedence) · CPC title

  • G06F21/575Primary

    Secure boot · CPC title

  • Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

  • electric · CPC title

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Frequently asked questions

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What does patent US11113402B2 cover?
Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is t…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F21/575. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).