Handling errors in buffers

Patent metadata

Field	Value
Publication number	US-11113164-B2
Application number	US-201816641387-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Oct 5, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

First claim

The invention claimed is:

1. An apparatus comprising:
a buffer comprising a plurality of entries to buffer items associated with data processing operations performed by at least one processing circuit; and
buffer control circuitry having a redundant allocation mode in which:
when allocating a given item to the buffer, the buffer control circuitry is configured to allocate the given item to each entry of a set of N redundant entries of the buffer, where N≥2; and
when reading or removing the given item from the buffer, the buffer control circuitry is configured to compare the items stored in said set of N redundant entries and to trigger an error handling response when a mismatch is detected between the items stored in said set of N redundant entries.

2. The apparatus according to claim 1 , comprising self-test control circuitry to trigger at least one of said at least one processing circuit to switch to a self-test state for executing a software self-test sequence of instructions.

3. The apparatus according to claim 1 , comprising at least one processing circuit supporting an intra-core lockstep mode in which the processing circuit is configured to perform redundant processing operations within a same processor pipeline and to perform error detection in dependence on a comparison of an outcome of the redundant processing operations.

4. The apparatus according to claim 1 , wherein the buffer control circuitry has a normal mode in which, when allocating a given item to the buffer, the buffer control circuitry is configured to allocate the given item to a single entry of the buffer.

5. The apparatus according to claim 4 , wherein the buffer control circuitry is configured to switch to the redundant allocation mode in response to entry of at least one processing circuit to a self-test state for executing a software self-test sequence of instructions.

6. The apparatus according to claim 5 , wherein the buffer control circuitry is configured to switch to the normal mode in response to a return to previous processing following execution of the software self-test sequence of instructions.

7. The apparatus according to claim 4 , comprising a configuration register to store a programmable control parameter for controlling whether the buffer control circuitry operates in the redundant allocation mode or the normal mode.

8. The apparatus according to claim 1 , wherein the buffer control circuitry is configured to operate in the redundant allocation mode when the at least one processing circuit is in a functional state for executing instructions other than a software self-test sequence of instructions.

9. The apparatus according to claim 1 , wherein the error handling response comprises updating a status register to indicate that an error has been detected.

10. The apparatus according to claim 1 , comprising a plurality of said buffers, wherein the error handling response comprises updating a status register to indicate which of the plurality of buffers encountered a detected error.

11. The apparatus according to claim 1 , comprising error detecting code storage circuitry to store at least one error detecting code corresponding to at least one of said set of N redundant entries, wherein when said mismatch is detected the buffer control circuitry is configured to detect which of the set of N redundant entries is an erroneous entry using said at least one error detecting code.

12. The apparatus according to claim 11 , wherein the error handling response comprises forwarding the item stored in one of said N redundant entries other than said erroneous entry for use in subsequent processing.

13. The apparatus according to claim 1 , wherein the buffer comprises an instruction queue to queue instructions processed by one of said at least one processing circuit.

14. The apparatus according to claim 1 , wherein the buffer comprises a load/store queue to queue load/store transactions issued in response to instructions executed by one of said at least one processing circuit.

15. The apparatus according to claim 1 , wherein the buffer comprises a buffer within a cache, to queue at least one of:
read requests to read data from the cache;
store data to be written to the cache in response to a store transaction issued by one of said at least one processing circuit;
linefill requests requesting that data is read from a further cache or memory;
linefill data read from the further cache or memory to be written to the cache; and
writeback requests requesting that data read from the cache is written to the further cache or memory.

16. The apparatus according to claim 1 , wherein the buffer comprises a transaction buffer in an interconnect or memory sub-system to buffer coherency transactions or memory access transactions.

17. The apparatus according to claim 1 , wherein the buffer is shared between a plurality of processing circuits.

18. A method comprising:
buffering items associated with data processing operations performed by at least one processing circuit in a plurality of entries of a buffer;
wherein when operating in a redundant allocation mode:
when allocating a given item to the buffer, the given item is allocated to each entry of a set of N redundant entries of the buffer, where N≥2; and
when reading or removing the given item from the buffer, the items stored in said set of N redundant entries are compared and an error handling response is triggered when a mismatch is detected between the items stored in said set of N redundant entries.

Assignees

• Advanced Risc Mach Ltd

Inventors

• VENU Balaji
• Boettcher Matthias Lothar
• Eyole Mbou

Classifications

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/2236 Primary

  to test CPU or processors · CPC title

• G06F11/186

  Passive fault masking when reading multiple copies of the same data · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F2201/805

  Real-time · CPC title