Store instruction to store instruction dependency

Patent metadata

Field	Value
Publication number	US-11113055-B2
Application number	US-201916357380-A
Country	US
Kind code	B2
Filing date	Mar 19, 2019
Priority date	Mar 19, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.

First claim

What is claimed is:

1. A computer-implemented method for creating a store instruction dependency in a processor pipeline comprising:
detecting, by a processor, a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction;
comparing, by the processor, the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction; and
writing, by the processor, a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
analyzing, by the processor and prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction; and
delaying, by the processor, the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction,
wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises:
translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction,
translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and
comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction.

2. The computer-implemented method of claim 1 , wherein the first store instruction is stored in a dispatch store table (DST).

3. The computer-implemented method of claim 1 , wherein the first store instruction is the youngest store instruction in a dispatch store table (DST).

4. The computer-implemented method of claim 3 , wherein an indicator bit is stored with the first store instruction in the DST.

5. The computer-implemented method of claim 4 , wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction is based on a presence of the indicator bit.

6. The computer-implemented method of claim 1 , wherein delaying the second store instruction comprises dynamically inserting a number of clock cycles between issue of the second store instruction and issue of the first store instruction.

7. A system for creating a store instruction dependency in a processor pipeline, the system comprising:
a processor communicatively coupled to a memory, the processor configured to:
detect a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction;
compare the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
write a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
analyze, prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction; and
delay the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction,
wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises:
translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction,
translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and
comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction.

8. The system of claim 7 , wherein the first store instruction is stored in a dispatch store table (DST).

9. The system of claim 7 , wherein the first store instruction is the youngest store instruction in a dispatch store table (DST).

10. The system of claim 9 , wherein the processor is further configured to store an indicator bit with the first store instruction in the DST.

11. The system of claim 10 , wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction is based on a presence of the indicator bit.

12. The system of claim 7 , wherein delaying the second store instruction comprises dynamically inserting a number of clock cycles between issue of the second store instruction and issue the first store instruction.

13. A computer program product for creating a store instruction dependency in a processor pipeline, the computer product comprising a computer readable storage medium having program instructions embodied therewith, the instructions executable by a processor to cause the processor to:
detect a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction;
compare the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
write a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
analyze, prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction; and
delay the second store instruction in the processor pipeline until a dependency is created betwe

Assignees

• IBM

Inventors

• Malley Edward
• Lee Jang-Soo
• Saporito Anthony
• Shum Chung-Lung K
• Alexander Gregory William

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3869

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title