Arrangement to calibrate a capacitive sensor interface

Patent metadata

Field	Value
Publication number	US-11112276-B2
Application number	US-201816491705-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	Mar 22, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

An arrangement (2) to calibrate a capacitive sensor interface (1) includes a capacitive sensor (10) having a capacitance (cmem, cmemsp, cmemsm) and a charge storing circuit (20) having a changeable capacitance (cdum, cdump, cdumm). A test circuit (30) applies a test signal (vtst) to the capacitive sensor (10) and the charge storing circuit (20). An amplifier circuit (40) has a first input connection (E40a) coupled to the capacitive sensor (10) and a second input connection (E40b) coupled to the charge storing circuit (20). The amplifier circuit (40) provides an output signal (Vout) in dependence on a first input signal (ΔVerr1) applied to the first input connection (E40a) and a second input signal (ΔVerr2) applied to the second input connection (E40b). A control circuit (60) is configured to trim the capacitance (cdum, cdump, cdumm) of the charge storing circuit (20) such that the level of the output signal (Vout) tends to the level of zero.

First claim

The invention claimed is:

1. A capacitive sensor arrangement, comprising:
a capacitive sensor;
a charge storing circuit having a changeable capacitance;
a test circuit configured to apply a test signal to the capacitive sensor and to the charge storing circuit;
an amplifier circuit having a first input coupled to the capacitive sensor and a second input coupled to the charge storing circuit, wherein the amplifier circuit is configured to provide an output signal at the output of the amplifier in response to application of the test signal to the capacitive sensor and to the charge storing circuit;,
a detection circuit configured to detect a level of the output signal; and
a control circuit coupled to the detection circuit and configured to trim the capacitance of the charge storing circuit such that the output signal tends to zero.

2. The arrangement as claimed in claim 1 ,
wherein the test circuit comprises a test signal generator configured to generate the test signal orthogonal to a sensor signal of the arrangement.

3. The arrangement as claimed in claim 1 ,
wherein the test circuit comprises a test signal generator configured to generate the test signal as a sequence of pulses.

4. The arrangement as claimed in claim 1 ,
further comprising a capacitor coupling the test circuit to the capacitive sensor and to the charge storing circuit.

5. The arrangement as claimed in claim 1 ,
wherein the capacitive sensor is a MEMS transducer and
the charge storing circuit comprises at least one changeable capacitor.

6. The arrangement as claimed in claim 5 , further comprising: a bias voltage source coupled to the capacitive sensor and to the charge storing circuit, wherein the bias voltage source is configured to apply a bias voltage to the capacitive sensor and to the charge storing circuit.

7. The arrangement as claimed in claim 1 , wherein the capacitive sensor is a differential MEMS transducer comprising a first capacitor and a second capacitor, a first node between the first capacitor and the second capacitor of the MEMS transducer coupled to the first input of the amplifier, the charge storing circuit comprising a first capacitor and a second capacitor, and a second node between the first capacitor and the second capacitor of the charge storing circuit coupled to the second input of the amplifier.

8. The arrangement as claimed in claim 1 , wherein the changeable capacitance comprises switchable capacitors, and the control circuit is configured to control the switchable capacitors ON and OFF using a digital dither.

9. The arrangement as claimed in claim 1 further comprising a sigma delta modulator, wherein the test signal generator is configured to generate the test signal based on a least significant bit generated by the sigma delta modulator.

10. A capacitive sensor interface circuit comprising:
a bias circuit coupleable to a charge storing circuit having a changeable capacitance and to a capacitive sensor, the bias circuit configured to apply a bias voltage to the charge storing circuit and to the capacitive sensor when the bias circuit is coupled to the capacitive sensor and to the charge storing circuit;
a test circuit coupleable to the charge storing circuit and to the capacitive sensor, the test circuit configured to apply a test signal to the charge storing circuit and to the capacitive sensor when the test circuit is coupled to the capacitive sensor and the charge storing circuit;
an amplifier circuit having a first input coupleable to the capacitive sensor and a second input coupleable to the charge storing circuit, wherein the amplifier circuit is configured to provide an output signal (Vout) at an output of the amplifier circuit in response to application of the test signal to the capacitive sensor and the charge string circuit;
a detection circuit configured to detect a level of the output signal (Vout);
a control circuit coupled to the detection circuit and configured to trim the capacitance of the charge storing circuit such that the level of the output signal (Vout) tends to zero when the test signal is applied to the charge storing circuit and to the capacitive sensor.

11. The interface circuit as claimed in claim 10 , wherein the test circuit comprises a test signal generator configured to generate the test signal as a sequence of pulses.

12. The interface circuit as claimed in claim 10 further comprising a sigma delta modulator, wherein the test signal generator is configured to generate the test signal based on a least significant bit generated by the sigma delta modulator.

13. The interface circuit as claimed in claim 10 further comprising a charge storing circuit having a changeable capacitance, the charge storing circuit coupled to the bias circuit and to the test circuit.

14. The interface circuit as claimed in claim 13 , wherein the changeable capacitance comprises switchable capacitors, and the control circuit is configured to control the switchable capacitors ON and OFF using a digital dither.

15. The interface circuit as claimed in claim 13 is an integrated circuit.

16. The interface circuit as claimed in claim 15 in combination with a capacitive transducer coupled to the bias circuit, wherein the capacitive sensor is a MEMS transducer.

17. A method in a capacitive sensor interface circuit, the method comprising: generating a bias signal for application to a capacitive sensor and to a charge storing circuit; generating a test signal for application to the capacitive sensor and the charge storing circuit when under bias;
generating a differential output signal based on input signals received from the capacitive sensor and the charge storing circuit in response to applying the test signal to the capacitive sensor and to the charge storing circuit;
detecting the differential output signal;
trimming a capacitance of the charge storing circuit using a control signal based on the detected differential output signal, wherein the control signal tends to reduce the differential signal to zero.

18. The method as claimed in claim 17 , wherein generating the test signal comprises generating a sequence of pulses.

19. The method as claimed in claim 17 , wherein generating the test signal comprises generating a sequence of pulses based on a least significant bit generated by a sigma delta modulator.

20. The method as claimed in claim 17 , wherein trimming the capacitance comprises digitally controlling an array of switchable capacitors of the charge storing circuit ON and OFF.

Assignees

• Knowles Electronics Llc

Inventors

• Steele Colin
• Scheuner Rene
• Christen Thomas
• Niederberger Mark

Classifications

• G01D5/24 Primary

  by varying capacitance · CPC title

• G01D18/00

  Testing or calibrating apparatus or arrangements provided for in groups G01D1/00 - G01D15/00 · CPC title