Physically unclonable function device with a load circuit to generate bias to sense amplifier

Patent metadata

Field	Value
Publication number	US-11108572-B2
Application number	US-201816158252-A
Country	US
Kind code	B2
Filing date	Oct 11, 2018
Priority date	Oct 11, 2018
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

A physically unclonable function (PUF) device is provided. The PUF device includes: a plurality of PUF cells configured to generate an output. Each of the plurality of cells includes a sense amplifier, a load circuit. The sense amplifier includes a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The sense amplifier having a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The first circuit generates an output at a first output node and the second circuit generates an output at the second output node. The load circuit having a first transistor and a second transistor configured to generate a bias to the sense amplifier to obtain a mask bit at a first output node and a second output node. The control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit. The harvester circuit includes a first transistor and a second transistor receives the input from the load and generates the difference in the input.

First claim

What is claimed is:

1. A physically unclonable function (PUF) device comprising:
a plurality of PUF cells, generating an output, wherein each of the plurality of PUF cells comprising:
a sense amplifier, comprising a first circuit and a second circuit coupled to a bit line and a complementary bit line,
wherein the first circuit generates an output at a first output node and the second circuit generates an output at a second output node;
a load circuit, comprising a first transistor, a second transistor, a first capacitor and a second capacitor to generate a bias to the sense amplifier to obtain a mask bit at the first output node and the second output node,
wherein the first transistor is coupled to one node of the first capacitor and another node of the first capacitor is coupled to a ground voltage,
the second transistor is coupled to one node of the second capacitor and another node of the second capacitor is coupled to a ground voltage,
a control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit,
wherein the load circuit generates a bias voltage to the sense amplifier to obtain the mask bit, the first transistor and the second transistor in the load circuit are selectively turned on by the first selection bit or the second selection bit, and the first transistor and the second transistor in the load circuit are not turned on at the same time by the first selection bit and the second selection bit.

2. The PUF device of claim 1 , wherein the load circuit further comprises:
the first transistor, coupled to the sense amplifier at the first output node, and
the second transistor, coupled to the sense amplifier at the second output node.

3. The PUF device of clair er comprising:
the first circuit comprising a first pair of transistors to generate an output at the first output node and coupled to the bit line through a third transistor.

4. The PUF device of claim 3 , wherein the sense amplifier further comprises:
the second circuit comprising a second pair of transistors to generate the output at the second output node and coupled to the complementary bit line through a fourth transistor.

5. The PUF device of claim 4 , further comprising:
a control terminal of the first pair of transistors are coupled to the second output node, and
a control terminal of the second pair of transistors are coupled to the first output node,
wherein the first pair of transistors and the second pair of transistors forms a cross coupled inverter.

6. The PUF device of claim 1 , wherein the sense amplifier further comprising:
a harvester circuit, comprising a first harvester transistor and a second harvester transistor, receives an input from the load and generates the difference in the input.

7. A physically unclonable function (PUF) device comprising:
a plurality of PUF cells, generating an output, wherein each of the plurality of PUF cells comprising:
a sense amplifier, comprising a first circuit and a second circuit coupled to a bit line and a complementary bit line,
wherein the first circuit generates an output at a first output node and the second circuit generates an output at a second output node;
a load circuit, comprising a first transistor and a second transistor to generate a bias to the sense amplifier to obtain a mask bit at the first output node and the second output node; and
a control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit,
wherein the load circuit generates a bias voltage to one of the first output node and the second output node of the sense amplifier to obtain the mask bit, the first transistor and the second transistor in the load circuit are selectively turned on by the first selection bit or the second selection bit, the first transistor and the second transistor in the load circuit are not turned on at the same time by the first selection bit and the second selection bit.

8. The PUF device of claim 7 , wherein the load circuit further comprises:
the first transistor, coupled to the sense amplifier at the first output node, and
the second transistor, coupled to the sense amplifier at the second output node.

9. The PUF device of claim 7 , further comprising:
the first circuit comprising a first pair of transistors to generate the output at the first output node and coupled to the bit line through a third transistor.

10. The PUF device of claim 7 , wherein the sense amplifier further comprises:
the second circuit comprising a plurality of transistors to generate output at the second output node and coupled to the complementary bit line through a fourth transistor.

11. The PUF device of claim 10 , further comprising:
a control terminal of the first pair of transistors are coupled to the second output node, and
a control terminal of the second pair of transistors are coupled to the first output node,
wherein the first pair of transistors and the second pair of transistors forms a cross coupled inverter.

12. The PUF device of claim 7 , further comprising:
a harvester circuit, comprising a first harvester transistor and a second harvester transistor, receives an input from the load and generates the difference in the input.

13. The PUF device of claim 7 , wherein the first transistor or the second transistor of the load circuit is operated in linear region.

14. A physically unclonable function (PUF) device comprising:
a plurality of sense amplifiers, comprising a first circuit and a second circuit coupled to a bit line and a complementary bit line;
a load circuit, generating a bias to the plurality of sense amplifiers to obtain a mask bit at the bit line and the complementary bit line,
a plurality of harvester circuit, respectively comprising a first harvester transistor and a second harvester transistor, receives an input from the load and generates the difference in the input,
wherein the load circuit generates a bias voltage to one of the bit line and the complementary bit line to obtain the mask bit, a first transistor and a second transistor in the load circuit are selectively turned on by the first selection bit or the second selection bit, the first transistor and the second transistor in the load circuit are not turned on at the same time by the first selection bit and the second selection bit.

15. The PUF device of claim 14 , wherein the load circuit comprises:
a first transistor, a second transistor, a first capacitor and a second capacitor,
wherein the first transistor is coupled to one node of the first capacitor and another node of the first capacitor is coupled to a ground voltage,
the second transistor is coupled to one node of the second capacitor and another node of the second capacitor is coupled to a ground voltage.

16. The PUF device of claim 14 , wherein the load circuit further comprises:
a first transistor and a second transistor to generate the bias to the sense amplifiers to obtain the mask bit at the bit line and the complementary bit line.

17. The PUF device of claim 14 , wherein the first transistor or the second transistor of the load circuit is operated in linear region.

18. The PUF device of claim 14 , wherein the sense amplifiers further comprise:
the first circuit comprising a plurality of first pairs of transistors to generate outputs at a plurality of first output nodes and coupled to the bit line through a plurality of third transistors sixth tr

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Shih-Lien Linus

Classifications

• G06F7/764 Primary

  Masking · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title