Routing assembly and system using same

Patent metadata

Field	Value
Publication number	US-11108176-B2
Application number	US-202017012079-A
Country	US
Kind code	B2
Filing date	Sep 4, 2020
Priority date	Jan 11, 2016
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

A routing assembly for an electronic device has a front face with an array of connectors ports and each of the connector ports contain a first connector mounted therein. A first end of a cable can be directly terminated to the first connectors and the cables can be embedded in a tray that is configured to extend toward a chip package. The cables extend from the tray and terminates to a second connector that can be electrically connected to the chip package so as to provide a communication path between the first connector and the second connector that substantially bypasses a supporting circuit board.

First claim

We claim:

1. A system, comprising:
a box with a front side;
a motherboard positioned in the box, the motherboard supporting a chip package;
a routing assembly positioned in the box, the routing assembly including a front face that defines a N by M matrix of connector ports, where N and M are at least 2, the front face positioned at the front side, the routing assembly including a tray extending from the front face, the motherboard positioned above the tray;
a plurality of first connectors positioned in the connector ports;
a plurality of cables positioned in the tray, each of the cables having a first end terminated to one of the plurality of first connectors and a second end the extends into the internal opening; and
a plurality of second connectors terminated to the second ends and positioned adjacent the chip package, the plurality of second connectors arranged in a pattern that extends along a side of the chip package, wherein the plurality of second connectors are configured to be electrically connected to the chip package so as to provide a signal path between the first connectors and the chip package that substantially avoids traveling through the motherboard.

2. The system of claim 1 , wherein the tray extends from the front face in a cantilevered manner.

3. The system of claim 1 , wherein the motherboard supports a second row of connectors ports with a plurality of fourth connectors positioned therein, the fourth connectors electrically connected to the motherboard, wherein the first connectors communicate with the chip package via the cables and the fourth connectors communicate with the chip package via traces in the motherboard.

4. The system of claim 1 , wherein the plurality of cables are in a preconfigured arrangement that positions the second connectors on two sides of the chip package.

5. The system of claim 1 , wherein the tray is formed of a conductive material.

6. The system of claim 1 , wherein the plurality of cables are in a preconfigured arrangement that positions the second connectors on four sides of the chip package.

7. The system of claim 1 , wherein N and M are both at least 4.

8. A system, comprising:
a box with a front side;
a circuit board positioned in the box, the circuit board supporting a chip package;
a routing assembly positioned in the box, the routing assembly including a front face that defines a N by M matrix of connector ports, where both N and M are at least 2, the front face positioned at the front side, the routing assembly including a tray extending from the front face;
a plurality of first connectors positioned in the connector ports;
a plurality of cables positioned in the tray, each of the cables having a first end terminated to one of the plurality of first connectors and a second end the extends to an edge of the tray; and
a plurality of second connectors terminated to the second ends and positioned adjacent the chip package, the second connectors arranged in a pattern that extends along a first side of the circuit board, wherein the plurality of second connectors are electrically connected to the chip package by a plurality of vias that extend between the first side and a second side opposite the first side so that a signal path between the first connectors and the chip package travels through the plurality of vias but otherwise substantially avoids traveling through the circuit board.

9. The system of claim 8 , wherein the tray extends from the front face in a cantilevered manner.

10. The system of claim 8 , wherein N and M are both at least 4.

11. The system of claim 8 , wherein the plurality of cables are in a preconfigured arrangement that positions the second connectors on four sides of the chip package.

12. The system of claim 8 , wherein the tray is formed of a conductive material.

13. The system of claim 8 , wherein the system is configured to support a 20 Gbps data rate.

Assignees

• Molex Llc

Inventors

• Lloyd Brian Keith
• Fitzgerald Gregory
• Reed Bruce
• Walz Gregory
• Isaac Ayman

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H05K7/1023

  co-operating by abutting, e.g. flat pack · CPC title

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• H01R12/79

  connecting to rigid printed circuits or like structures · CPC title

• H01R12/73

  connecting to other rigid printed circuits or like structures · CPC title