Dual-gate transistors and their integrated circuits and preparation method thereof

Patent metadata

Field	Value
Publication number	US-11107900-B2
Application number	US-202016854016-A
Country	US
Kind code	B2
Filing date	Apr 21, 2020
Priority date	Apr 23, 2019
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption. Moreover, no additional power sources are added to the circuit, which makes it suitable for ultra-large-scale integrated circuits.

First claim

What is claimed is:

1. A dual-gate transistor, comprising:
an insulating substrate;
a semiconductor layer on the insulating substrate; and
at least one P-type transistor or at least one N-type transistor,
wherein the semiconductor layer includes a plurality of channel regions separated from each other, wherein each of the plurality of channel regions is provided with a P-type transistor or an N-type transistor,
wherein the P-type transistor includes:
a pair of contact electrodes on the channel region, wherein one of the electrodes is a source electrode connected to VDD and the other one of the electrodes is a drain electrode,
a gate dielectric layer between the pair of contact electrodes;
a main gate electrode on the gate dielectric layer near the source electrode; and
an auxiliary gate electrode near the drain electrode connected to GND,

wherein the N-type transistor includes:
a pair of contact electrodes on the channel region, wherein one of the electrodes is a source electrode connected to GND and the other one of the electrodes is a drain electrode,
a gate dielectric layer between the pair of electrodes;
a main gate electrode on the gate dielectric layer near the source electrode; and
an auxiliary gate electrode near the drain electrode connected to VDD,

wherein the auxiliary gate electrodes of P-type transistor and N-type transistor are respectively connected with GND and VDD.

2. The dual-gate transistor of claim 1 , wherein the insulating substrate comprises silicon/silicon dioxide, quartz, glass, Al 2 O 3 , PET, PEN, or PI.

3. The dual-gate transistor of claim 1 , wherein the semiconductor layer includes one or more materials comprising semiconducting-type carbon nanotubes, graphene nano ribbons, MoS 2 , WS 2 , black phosphorus, Si, Ge, InAs, InSb, PbS, Pb Se, or PbTe, wherein the semiconductor layer is formed by a single layer composed of one of the materials or a composite layer composed of two or more of the materials.

4. The dual-gate transistor of claim 1 , wherein the semiconductor layer has a bandgap smaller than 1 eV.

5. The dual-gate transistor of claim 1 , wherein the pair of contact electrodes, the main gate electrode and auxiliary gate electrodes in the P-type transistor or the N-type transistor includes one or more materials comprising Pd, Pt, Ta, Ti, Cr, Ca, Cu, Al, Au, W, Y, Sc, conductive metal silicide, and doped polysilicon.

6. The dual-gate transistor of claim 1 , wherein the gate dielectric layer material in the P-type transistor or the N-type transistor includes a high-κ oxide insulating material, wherein the high-κ oxide insulating material includes Al 2 O 3 , HfO 2 , Y 2 O 3 , Zr 2 O 3 , wherein interlayer interconnections are formed by a low-κ insulating material comprising SiO 2 , SiC, or PMMA, wherein the high-κ insulating material has a κ value greater than 3.9, and the low-κ insulating material has a κ value less to 3.9.

7. The dual-gate transistor of claim 1 , wherein the auxiliary gate electrode in the P-type transistor is made of a high work-function metal including Pd or Ta, wherein the auxiliary gate electrode in the N-type transistor is made of a low work-function metal including Sc or Ti.

8. An integrated circuit, comprising a dual-gate transistor of claim 1 .

Assignees

• Univ Beijing

Inventors

• Zhao Chenyi
• Zhong Donglai
• Zhang Zhiyong
• Peng Lianmao

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title