Integrated circuit device including complementary metal-oxide-semiconductor transistor with field cut regions to increase carrier mobility

Patent metadata

Field	Value
Publication number	US-11107882-B2
Application number	US-201916453228-A
Country	US
Kind code	B2
Filing date	Jun 26, 2019
Priority date	Nov 27, 2018
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

An integrated circuit device includes a substrate including a first conductivity type region and a second conductivity type region, a first active region arranged in the second conductivity type region, a second active region arranged in the first conductivity type region and spaced apart from the first active region with an isolation region between the second active region and the first active region, an isolation film formed in the isolation region, and a first field cut region extending along the isolation region in a first direction parallel with a channel length direction of each of a first conductivity type transistor on the first active region and a second conductivity type transistor on the second active region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate comprising a first conductivity type region and a second conductivity type region;
at least one first active region comprising at least one first conductivity type transistor in the second conductivity type region;
at least one second active region comprising at least one second conductivity type transistor in the first conductivity type region, the at least one second active region being spaced apart from the at least one first active region with an isolation region between the at least one second active region and the at least one first active region;
an isolation film in the isolation region;
a first field cut region extending in the isolation region along a first direction that is parallel with a channel length direction of the at least one first conductivity type transistor and the at least one second conductivity type transistor;
a second field cut region spaced apart from the first field cut region with the at least one first active region between the second field cut region and the first field cut region; and
a third field cut region spaced apart from the first field cut region with the at least one second active region between the third field cut region and the first field cut region,
wherein, in a plan view, the second field cut region comprises a first protrusion protruding toward the first field cut region, and
wherein, in the plan view, the third field cut region comprises a second protrusion protruding toward the first field cut region.

2. The integrated circuit device of claim 1 , wherein the isolation film comprises:
a first isolating portion between the at least one first active region and the first field cut region and defining respective boundaries of the at least one first active region and the first field cut region, the first isolating portion having a first width that is less than a width of the isolation region; and
a second isolating portion between the at least one second active region and the first field cut region and defining respective boundaries of the at least one second active region and the first field cut region, the second isolating portion having a second width that is less than the width of the isolation region.

3. The integrated circuit device of claim 1 , wherein the first field cut region comprises a portion of the substrate that is free of transistors and is in the second conductivity type region, wherein the first field cut region divides the isolation film into multiple portions having respective widths that are less than a width of the isolation region in a direction perpendicular to the channel length direction.

4. The integrated circuit device of claim 1 , further comprising an isolated well in the first field cut region and comprising a second conductivity type doped region having a higher doping concentration than the second conductivity type region.

5. The integrated circuit device of claim 1 , wherein:
the at least one first conductivity type transistor comprises a first gate and a first channel extending in the channel length direction;
the at least one second conductivity type transistor comprises a second gate and a second channel extending in the channel length direction; and
the first field cut region comprises an isolated well electrically connected to at least one of the first gate and the second gate.

6. The integrated circuit device of claim 1 , wherein the second field cut region is in the second conductivity type region, and
the third field cut region is in the first conductivity type region.

7. The integrated circuit device of claim 1 , further comprising:
a first dummy active region in a region that is free of transistors between the first field cut region and the second field cut region; and
a second dummy active region in a region that is free of transistors between the first field cut region and the third field cut region.

8. The integrated circuit device of claim 1 , further comprising:
a first guard ring at least partially surrounding the at least one first conductivity type transistor and spaced apart from the first field cut region; and
a second guard ring at least partially surrounding the at least one second conductivity type transistor and spaced apart from the first field cut region,
wherein the first guard ring and the second guard ring are at a periphery of or outside the isolation region.

9. The integrated circuit device of claim 8 , wherein the first guard ring comprises a second conductivity type doped region in the second conductivity type region, and
the second guard ring comprises a first conductivity type doped region in the first conductivity type region.

10. The integrated circuit device of claim 1 , wherein each of the first protrusion and the second protrusion is arranged in a region of the substrate, the region having no circuits arranged therein.

11. An integrated circuit device comprising:
a substrate comprising an n-type region and a p-type region;
a first active region in the n-type region;
a second active region in the p-type region, the second active region being spaced apart from the first active region in a first direction with an isolation region between the second active region and the first active region;
an isolation film in the isolation region;
a first field cut region in the n-type region in the isolation region and extending along a second direction perpendicular to the first direction;
a second field cut region spaced apart from the first field cut region with the first active region between the second field cut region and the first field cut region; and
a third field cut region spaced apart from the first field cut region with the second active region between the third field cut region and the first field cut region,
wherein, in a plan view, the second field cut region comprises a first protrusion protruding toward the first field cut region, and
wherein, in the plan view, the third field cut region comprises a second protrusion protruding toward the first field cut region.

12. The integrated circuit device of claim 11 , wherein the first field cut region comprises a portion of the n-type region of the substrate, and wherein the isolation film comprises:
a first isolating portion between the first active region and the first field cut region, the first isolating portion having a first width that is less than a width of the isolation region in the first direction; and
a second isolating portion between the second active region and the first field cut region, the second isolating portion having a second width that is less than the width of the isolation region in the first direction.

13. The integrated circuit device of claim 12 , wherein the first and second active regions comprise transistors therein having respective channel lengths extending in the second direction, the transistors comprising a first gate on the first active region, and a second gate on the second active region, the integrated circuit device further comprising:
an isolated well in the first field cut region; and
a wiring structure configured to apply a voltage to the isolated well and to at least one of the first gate or the second gate.

14. The integrated circuit device of claim 13 , wherein the isolated well is electrically connected to at least one of the first gate or the second gate.

15. The integrated circuit device of claim 11 , further comprising:
a first guard ring spaced apart from the first field cut region with the first active region between the first guard ring and the first field cut region; and
a second

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Jae-Joon

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0188 Primary

  Manufacturing their isolation regions · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/859 Primary

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title