Single-wire bus (SuBUS) slave circuit and related apparatus

Patent metadata

Field	Value
Publication number	US-11106615-B2
Application number	US-202016736164-A
Country	US
Kind code	B2
Filing date	Jan 7, 2020
Priority date	Jan 16, 2019
Publication date	Aug 31, 2021
Grant date	Aug 31, 2021

Abstract

A single-wire bus (SuBUS) slave circuit is provided. The SuBUS slave circuit is coupled to a SuBUS bridge circuit via a SuBUS and can be configured to perform a slave task that may block communication on the SuBUS. Notably, the SuBUS slave circuit may not be equipped with an accurate timing reference source that can determine a precise timing for terminating the slave task and unblock the SuBUS. Instead, the SuBUS slave circuit is configured to terminate the slave task and unblock the SuBUS based on a self-determined slave free-running-oscillator count derived from a start-of-sequence training sequence that precedes any SuBUS telegram of a predefined SuBUS operation, even though the SuBUS operation is totally unrelated to the slave task. As such, it may be possible to eliminate the accurate timing reference source from the SuBUS slave circuit, thus helping to reduce cost and current drain in the SuBUS slave circuit.

First claim

What is claimed is:

1. A single-wire bus (SuBUS) slave circuit comprising:
a front-end circuit coupled to a SuBUS and configured to receive a start-of-sequence (SOS) training sequence corresponding to a synchronization interval and preceding a SuBUS telegram corresponding to a predefined SuBUS operation comprising at least one of a register-read operation and a register-write operation; and
a digital control circuit coupled to the front-end circuit and configured to:
control the front-end circuit to enable a slave task unrelated to the predefined SuBUS operation indicated by the SuBUS telegram during a predefined slave task interval; and
control the front-end circuit to disable the slave task at an expiration of the predefined slave task interval based on the synchronization interval.

2. The SuBUS slave circuit of claim 1 wherein the digital control circuit is further configured to:
control the front-end circuit to enable an impedance measurement operation during the predefined slave task interval; and
control the front-end circuit to disable the impedance measurement operation at the expiration of the predefined slave task interval.

3. The SuBUS slave circuit of claim 1 wherein the digital control circuit is further configured to:
control the front-end circuit to enable a non-volatile memory read operation during the predefined slave task interval; and
control the front-end circuit to disable the non-volatile memory read operation at the expiration of the predefined slave task interval.

4. The SuBUS slave circuit of claim 1 wherein the digital control circuit is further configured to:
count a plurality of free-running oscillator (FRO) pulses during the synchronization interval;
determine a slave FRO count during the predefined slave task interval based on the plurality of FRO pulses counted during the synchronization interval;
control the front-end circuit to enable the slave task independent of the predefined SuBUS operation during the predefined slave task interval; and
control the front-end circuit to disable the slave task in response to the slave FRO count indicating the expiration of the predefined slave task interval.

5. The SuBUS slave circuit of claim 4 wherein the digital control circuit comprises:
a digital controller configured to:
control the front-end circuit to enable the slave task independent of the predefined SuBUS operation during the predefined slave task interval; and
control the front-end circuit to disable the slave task in response to receiving an indication signal; and

a timer configured to provide the indication signal to the digital controller in response to the slave FRO count indicating the expiration of the predefined slave task interval.

6. The SuBUS slave circuit of claim 5 wherein the digital control circuit further comprises a demodulator configured to:
count the plurality of FRO pulses during the synchronization interval; and
derive the slave FRO count during the predefined slave task interval based on the count of the plurality of FRO pulses during the synchronization interval.

7. The SuBUS slave circuit of claim 1 further comprising an analog circuit configured to perform the slave task during the predefined slave task interval.

8. The SuBUS slave circuit of claim 7 wherein:
the analog circuit comprises an impedance sensor configured to perform an impedance measurement operation during the predefined slave task interval; and
the digital control circuit is further configured to:
control the front-end circuit to enable the impedance sensor to perform the impedance measurement operation during the predefined slave task interval; and
control the front-end circuit to disable the impedance measurement operation in response to the slave FRO count indicating the expiration of the predefined slave task interval.

9. The SuBUS slave circuit of claim 7 wherein:
the analog circuit comprises a memory controller configured to perform a non-volatile memory read operation during the predefined slave task interval; and
the digital control circuit is further configured to:
control the front-end circuit to enable the memory controller to perform the non-volatile memory read operation during the predefined slave task interval; and
control the front-end circuit to disable the non-volatile memory read operation in response to the slave FRO count indicating the expiration of the predefined slave task interval.

10. The SuBUS slave circuit of claim 7 wherein the digital control circuit is further configured to control the front-end circuit to provide a higher charging current to the analog circuit for performing the slave task during the predefined slave task interval.

11. A single-wire bus (SuBUS) apparatus comprising:
a SuBUS bridge circuit;
a SuBUS coupled to the SuBUS bridge circuit; and
a SuBUS slave circuit comprising:
a front-end circuit coupled to the SuBUS and configured to receive a start-of-sequence (SOS) training sequence corresponding to a synchronization interval and preceding a SuBUS telegram corresponding to a predefined SuBUS operation comprising at least one of a register-read operation and a register-write operation; and
a digital control circuit coupled to the front-end circuit and configured to:
control the front-end circuit to enable a slave task unrelated to the predefined SuBUS operation indicated by the SuBUS telegram during a predefined slave task interval; and
control the front-end circuit to disable the slave task at an expiration of the predefined slave task interval based on the synchronization interval.

12. The SuBUS apparatus of claim 11 wherein the digital control circuit is further configured to:
control the front-end circuit to enable an impedance measurement operation during the predefined slave task interval; and
control the front-end circuit to disable the impedance measurement operation at the expiration of the predefined slave task interval.

13. The SuBUS apparatus of claim 11 wherein the digital control circuit is further configured to:
control the front-end circuit to enable a non-volatile memory read operation during the predefined slave task interval; and
control the front-end circuit to disable the non-volatile memory read operation at the expiration of the predefined slave task interval.

14. The SuBUS apparatus of claim 11 wherein the digital control circuit is further configured to:
count a plurality of free-running oscillator (FRO) pulses during the synchronization interval;
determine a slave FRO count during the predefined slave task interval based on the plurality of FRO pulses counted during the synchronization interval;
control the front-end circuit to enable the slave task independent of the predefined SuBUS operation during the predefined slave task interval; and
control the front-end circuit to disable the slave task in response to the slave FRO count indicating the expiration of the predefined slave task interval.

15. The SuBUS apparatus of claim 14 wherein the digital control circuit comprises:
a digital controller configured to:
control the front-end circuit to enable the slave task independent of the predefined SuBUS operation during the predefined slave task interval; and
control the front-end circuit to disable the slave task in response to receiving an indication signal; and

a timer configured to provide the indication signal to the digital controller in response to the slave FRO count indicating the expiration of the predefined slave task interval.

16. The SuBUS apparatus of claim 15 wherein the digital control circuit further comp

Assignees

• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Hietala Alexander Wayne
• Nipunage Puneet Paresh

Classifications

• H04L12/40006

  Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90) · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title