Semiconductor memory device and method for adjusting threthold voltage thereof

Patent metadata

Field	Value
Publication number	US-11100975-B2
Application number	US-202016803260-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Sep 19, 2019
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of memory cells connected to a word line;
a circuit configured to apply a voltage to the word line;
a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first single slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second single slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope; and
a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

2. The semiconductor memory device according to claim 1 , wherein each of the first signal and the second signal is a ramp signal.

3. The semiconductor memory device according to claim 1 , wherein the first signal is a pulse signal and the second signal is a ramp signal.

4. The semiconductor memory device according to claim 1 , further comprising:
a counter configured to:
start counting when a voltage starts to be applied to the word line; and
output a count value;

a division circuit configured to output a division value obtained by dividing the count value by a value corresponding to a slope with which the voltage is increased; and
a digital/analog conversion circuit configured to perform digital/analog conversion of the division value and output the digital/analog-converted division value as the first signal or the second signal.

5. The semiconductor memory device according to claim 1 , further comprising: an analog voltage generation circuit configured to generate an analog signal including the first signal or the second signal.

6. A semiconductor memory device comprising:
a word line;
a circuit configured to apply a ramp signal to the word line, the ramp signal including a voltage that increases based on a predetermined slope;
a plurality of memory cells connected to the word line, wherein the memory cells are grouped into a plurality of groups based on a respective length of the word line from the circuit to each of the memory cells;
a calculation circuit configured to calculate, for each of the groups, a difference between an expected value of a threshold voltage corresponding to data stored in a memory cell belonging to each of the groups and a detected threshold voltage of the memory cell;
a shift circuit configured to shift, for each of the groups, a determination voltage for determining the threshold voltage corresponding to the data stored in the memory cell based on the calculated difference
a counter configured to output a first count value starting to be counted when the ramp signal is applied to the word line,
wherein the calculation circuit is configured to use the first count value counted by the counter until a current flows through the memory cell after applying the ramp signal as a detected threshold voltage for the memory cell, and calculate a count value difference between the expected value of the threshold voltage and the first count value, and
the shift circuit configured to shift the determination voltage to a second count value based on the calculated count value difference.

7. The semiconductor memory device according to claim 6 , wherein the shift circuit is further configured to shift the determination voltage to the second count value when the count value difference exceeds a predetermined value.

8. A method of operating a semiconductor memory device including a plurality of memory cells connected to a word line, comprising:
applying a voltage to the word line;
detecting a first time difference from when a first signal that increases with a first single slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal that increases with a second single slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope; and
determining a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

9. The method according to claim 8 , wherein each of the first signal and the second signal is a ramp signal.

10. The method according to claim 8 , wherein the first signal is a pulse signal and the second signal is a ramp signal.

11. The method according to claim 8 , further comprising:
starting counting when a voltage starts to be applied to the word line;
outputting a division value obtained by dividing a count value by a value corresponding to a slope with which the voltage is increased; and
performing digital/analog conversion of the division value and outputting the digital/analog-converted division value as the first signal or the second signal.

12. The method according to claim 8 , further comprising: generating an analog signal including the first signal or the second signal.

13. A method of operating a semiconductor memory device including a plurality of memory cells connected to a word line, the plurality of memory cells being grouped into a plurality of groups based on a respective length of the word line from a circuit configured to apply a ramp signal to the word line to each of the memory cells,
the method comprising:
applying the ramp signal to the word line, the ramp signal including a voltage increasing with a predetermined slope;
calculating, for each of the groups, a difference between an expected value of a threshold voltage corresponding to data stored in a memory cell belonging to each of the plurality of groups and a detected threshold voltage of the memory cell;
shifting, for each of the groups, a determination voltage for determining the threshold voltage corresponding to the data stored in the memory cell based on the calculated difference;
outputting a first count value starting to be counted when the ramp signal is applied to the word line,
using the first count value counted until a current flows through the memory cell after applying the ramp signal as a detected threshold voltage for the memory cell,
calculating a count value difference between the expected value of the threshold voltage and the first count value, and
shifting the determination voltage to a second count value based on the calculated count value difference.

14. The method according to claim 13 , further comprising: shifting the determination voltage to the second count value when the count value difference exceeds a predetermined value.

Assignees

• Kioxia Corp

Inventors

• Ito Rui
• Morimoto Makoto
• Shimizu Yutaka
• Fujimoto Ryuichi

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C16/32

  Timing circuits · CPC title