Throttling of components using priority ordering

Patent metadata

Field	Value
Publication number	US-11099628-B2
Application number	US-201816144919-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

An apparatus is provided, where the apparatus includes a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities. The apparatus further includes logic to selectively throttle one or more of the plurality of components. In an example, an order in which the one or more of the plurality of components are to be throttled may be based on the plurality of throttling priorities.

First claim

We claim:

1. An apparatus comprising:
a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities; and
a first logic to receive one or more parameters indicative of the plurality of throttling priorities, and to selectively throttle one or more of the plurality of components, wherein an order in which the one or more of the plurality of components are to be throttled is based on the plurality of throttling priorities; and
a second logic to respectively assign the plurality of throttling priorities to the corresponding plurality of components, based on input received from one or more of: an Operating System (OS), Basic Input/Output System (BIOS), or a User Interface,

wherein when the input is received from the OS;
the OS is to store the input to one or more registers; and
the second logic is to receive the input from the one or more registers, and to respectively assign the plurality of throttling priorities to the corresponding plurality of components based on the input received from the OS via the one or more registers.

2. The apparatus of claim 1 , wherein:
a first component of the plurality of components has a first throttling priority;
a second component of the plurality of components has a second throttling priority that is lower than the first throttling priority; and
the first logic is to throttle the first component prior to the second component, in response to the second throttling priority being lower than the first throttling priority.

3. The apparatus of claim 1 , wherein:
the first logic is to order the plurality of components in a first order, based on an order of the corresponding plurality of throttling priorities; and
the one or more of the plurality of components are to be throttled in the first order.

4. The apparatus of claim 3 , wherein:
the first order corresponds to a descending order of the plurality of throttling priorities.

5. The apparatus of claim 3 , wherein:
the first logic is to un-throttle the one or more of the plurality of components in a second order that is opposite of the first order.

6. The apparatus of claim 1 , further comprising:
a circuitry to update a headroom parameter that is representative of constraint headroom available to the plurality components,
wherein the first logic is to throttle a component, in response to the headroom parameter being lower than a threshold value.

7. The apparatus of claim 6 , wherein the constraint headroom is based on a power budget available to the plurality components and a sum of power consumed by the plurality components.

8. The apparatus of claim 6 , wherein:
a first component of the plurality of components has a corresponding first throttling scaling coefficient; and
in response to the first component being throttled, the first component is to reduce an operating frequency of the first component by a product of: the first throttling scaling coefficient and the headroom parameter.

9. The apparatus of claim 1 , wherein:
a first component of the plurality of components comprises a first plurality of circuitries within a first voltage or frequency domain; and
a second component of the plurality of components comprises a second plurality of circuitries within a second voltage or frequency domain.

10. The apparatus of claim 1 , further comprising:
one or more registers to store the plurality of throttling priorities.

11. A system comprising:
a memory to store instructions;
a processor coupled to the memory, the processor to execute the instructions;
a wireless interface to facilitate communication between the processor and another system,
wherein at least one of a plurality of components of the system has a corresponding throttling priority of a plurality of throttling priorities, and
wherein the plurality of components includes one or more of: the memory, the processor, or the wireless interface; and

a first logic to throttle a first component of the plurality of components, based on the plurality of throttling priorities; and
a second logic to respectively assign the plurality of throttling priorities to the corresponding plurality of components, based on input received from one or more of: an Operating System (OS), Basic Input/Output System (BIOS), or a User Interface, wherein when the input is received from the OS:
the OS is to store the input to one or more registers; and
the second logic is to receive the input from the one or more registers, and to respectively assign the plurality of throttling priorities to the corresponding plurality of components based on the input received from the OS via the one or more registers.

12. The system of claim 11 , wherein the first logic is to:
determine that the first component has a highest throttling priority among the throttling priorities of components that have not been throttled; and
select the first component for throttling, based on the first component having the highest throttling priority.

13. The system of claim 11 , wherein the first logic is to:
receive a parameter that is indicative of a difference between: a budget available to the plurality components, and a sum of consumption by the plurality components, wherein the budget is one of: a power budget, a current budget, or a reliability budget.

14. The system of claim 13 , wherein the first logic is to:
throttle the first component, in response to the parameter being less than a threshold value.

15. The system of claim 13 , wherein the first logic is to:
receive a throttling scaling coefficient corresponding to the first component; and
throttle the first component to reduce an operating frequency of the first component by a product of: the throttling scaling coefficient and the parameter.

16. The system of claim 13 , wherein the first logic is to:
throttle the first component to reduce an input voltage to the first component.

17. Non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to:
receive a plurality of throttling priorities for a corresponding plurality of components; and
determine a sequence in which the components of the plurality are to be throttled, based on the plurality of throttling priorities; and
respectively assign the plurality of throttling priorities to the corresponding plurality of components, based on input received from one or more of: an Operating System (OS), Basic Input/Output System (BIOS), or a User Interface, wherein when the input is received from the OS:
the OS is to store the input to one or more registers; and
the processor is to receive the input from the one or more registers, and to respectively assign the plurality of throttling priorities to the corresponding plurality of components based on the input received from the OS via the one or more registers.

18. The non-transitory computer-readable storage media of claim 17 , wherein:
the sequence in which the components are to be throttled is based on a corresponding descending sequence of the plurality of throttling priorities.

19. The non-transitory computer-readable storage media of claim 17 , wherein:
a first component of the plurality of components is assigned a first throttling priority;
a second component of the plurality of components is assigned a second throttling priority that is lower than the first throttling priority; and
the first component is throttled prior to the second component, in response to the second throttling priority

Assignees

• Intel Corp

Inventors

• Ananthakrishnan Avinash
• Shrall Jeremy

Classifications

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title