Power saving for type-C connectors

Patent metadata

Field	Value
Publication number	US-11099623-B2
Application number	US-201916458024-A
Country	US
Kind code	B2
Filing date	Jun 29, 2019
Priority date	Jun 29, 2019
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

First claim

We claim:

1. An apparatus comprising:
an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port;
a first circuitry to place toggled values on the CC signal path; and
a second circuitry to couple the ground signal path to a detection signal path,
wherein the placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device; and
wherein the placement of the toggled values on the CC signal path is disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device, wherein the apparatus further comprises:
a software-controllable signal coupled to the second circuitry, wherein, upon the software-controllable signal having a predetermined value, the second circuitry is to place the first value on the detection signal path.

2. The apparatus of claim 1 ,
wherein the first circuitry is part of a Power Delivery (PD) controller.

3. The apparatus of claim 1 ,
wherein a power delivered to the first circuitry is disabled when the detection signal path carries the second value.

4. The apparatus of claim 1 ,
wherein the CC signal path is a first CC signal path; and
wherein the interface is also to a second CC signal path.

5. The apparatus of claim 4 ,
wherein the first circuitry is to place toggled values on the second CC signal path;
wherein the placement of the toggled values on the second CC signal path is enabled when the detection signal path carries the first value; and
wherein the placement of the toggled values on the second CC signal path is disabled when the detection signal path carries the second value.

6. The apparatus of claim 1 ,
wherein the detection signal path is coupled by a resistor element to a power supply voltage rail V cc .

7. The apparatus of claim 1 , wherein the detection signal path is pulled up to a power supply level by default via a pull-up resistor.

8. The apparatus of claim 1 , wherein a power controller toggles the CC signal path to establish orientation and/or role identification when the detections signal path carries the first value.

9. The apparatus of claim 1 comprising one or more shield pins that are connected to ground, wherein the shield pins are configured to provide return current carrying capability.

10. A system comprising a memory, a processor coupled to the memory, and a wireless interface to allow the processor to communicate with another device, the processor including:
an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port;
a first circuitry to place toggled values on the CC signal path; and
a second circuitry to couple the ground signal path to a detection signal path,
wherein the placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device; and
wherein the placement of the toggled values on the CC signal path is disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device, wherein the processor further comprises:
a software-controllable signal coupled to the second circuitry, wherein, upon the software-controllable signal having a predetermined value, the second circuitry is to place the first value on the detection signal path.

11. The system of claim 10 ,
wherein the first circuitry is part of a Power Delivery (PD) controller.

12. The system of claim 10 ,
wherein a power delivered to the first circuitry is disabled when the detection signal path carries the second value.

13. The system of claim 10 ,
wherein the CC signal path is a first CC signal path; and
wherein the interface is also to a second CC signal path.

14. The system of claim 13 ,
wherein the first circuitry is to place toggled values on the second CC signal path;
wherein the placement of the toggled values on the second CC signal path is enabled when the detection signal path carries the first value; and
wherein the placement of the toggled values on the second CC signal path is disabled when the detection signal path carries the second value.

15. The system of claim 10 ,
wherein the detection signal path is coupled by a resistor element to a power supply voltage rail V cc .

16. A method comprising:
placing toggled values on a Configuration Channel (CC) signal path of an interface to a Universal Serial Bus (USB) Type-C connector port; and
coupling a ground signal path of the interface to the USB Type-C connector port to a detection signal path,
wherein the placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device; and
wherein the placement of the toggled values on the CC signal path is disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device, wherein the method further comprising:
placing the first value on the detection signal path upon a software-controllable signal having a predetermined value.

17. The method of claim 16 ,
wherein the toggled values are placed on the CC signal path of the interface via a CC logic; and
wherein the detection signal path is coupled by a resistor element to a power supply voltage rail V cc .

18. The method of claim 17 ,
wherein a power delivered to the CC logic is disabled when the detection signal path carries the second value.

19. The method of claim 16 ,
wherein the CC signal path is a first CC signal path; and
wherein the interface is also to a second CC signal path.

20. The method of claim 19 , comprising:
placing toggled values on the second CC signal path;
wherein the placement of the toggled values on the second CC signal path is enabled when the detection signal path carries the first value; and
wherein the placement of the toggled values on the second CC signal path is disabled when the detection signal path carries the second value.

Assignees

• Intel Corp

Inventors

• K Tarakesava Reddy
• Alaparthi Phani K
• K S S Ranganadh
• Chahar Shobhit

Classifications

• H02J7/90

  Regulation of charging or discharging current or voltage · CPC title

• H02J9/005

  using a power saving mode (for copiers G03G15/5004) · CPC title

• H01R2107/00

  Four or more poles · CPC title

• H01R24/60

  Contacts spaced along planar side wall transverse to longitudinal axis of engagement · CPC title

• G06F1/3253 Primary

  Power saving in bus · CPC title