Printed circuit board with edge soldering for high-density packages and assemblies

US11096290B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11096290-B2
Application numberUS-201816150713-A
CountryUS
Kind codeB2
Filing dateOct 3, 2018
Priority dateOct 23, 2015
Publication dateAug 17, 2021
Grant dateAug 17, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of fabricating an integrated circuit assembly, or IC assembly, comprising: providing at least two IC packages, each IC package comprising: a PCB, said PCB having: two opposite main surfaces, each delimited by lateral edges and having lateral surfaces, each lateral surface meeting each of the main surfaces at one of the lateral edges; a row of solder pads extending along a lateral edge of the PCB, with each solder pad of the row formed directly at said lateral edge and/or directly on one of the lateral surfaces meeting one of the two main surfaces at said lateral edge; and an integrated circuit (IC) chip mounted on the PCB, such that a main surface of the IC chip faces and electrically connects terminals on said main surface of the IC chip to terminals on an opposite one of the two main surfaces of the PCB, wherein said method further comprises: mounting the at least two IC packages such that a main surface of one of the at least two IC packages is parallel to and faces a main surface of another one of the at least two IC packages provided; and soldering each PCB of the at least two IC packages to a same board via a respective row of solder pads formed directly at a lateral edge of said each PCB and/or directly on a lateral surface meeting one of the two main surfaces at said one lateral edge of said each PCB, wherein each PCB of the at least two IC packages is edge-soldered to the same board via a respective row of solder pads formed directly at the lateral edge and/or directly on one lateral surface of said each PCB, and said method of fabricating an IC assembly further comprising: providing a third integrated circuit package, or third IC package, between each of said at least two IC packages, wherein the third integrated circuit package comprises: a printed circuit board, or PCB, and an integrated circuit chip, or IC chip, mounted on the PCB of the third IC package, a main surface of the lC chip of the third IC package facing and electrically connecting a main surface of the PCB of the third IC package, and a heat dissipating structure comprising one or more thermally conducting layers, each intercalated between adjacent IC packages of the IC assembly. 2. The method of claim 1 , wherein the fabricating a row of solder pads comprises fabricating a row of holes on a main surface of the PCB, so as for the row to extend along an initial lateral edge, bridging said main surface and an initial lateral surface of the provided PCB; and cutting the provided PCB along the initial lateral edge to obtain a new lateral edge and a new lateral surface, so as for each hole of the row to be cut open at said new lateral surface as obtained after cutting, which meets said one of the two main surfaces at the new lateral edge. 3. The method of claim 2 , wherein the fabricating a row of solder pads further comprises, prior to cutting: drilling through holes and plating or filling the drilled through holes with an electrically conducting material to obtain the solder pads. 4. The method of claim 2 , wherein the fabricating a row of solder pads further comprises, prior to cutting: drilling blind holes and plating the drilled, blind holes with an electrically conducting material to obtain the solder pads. 5. The method of claim 4 , wherein the steps of drilling and plating are carried out on each of the two main surfaces of the provided PCB, so as to obtain, after cutting the PCB, a first row of solder pads and a second row of solder pads, the second row extending opposite to the first row. 6. The method of claim 1 , wherein said third IC package further comprises: one thermally conducting layer provide mechanical and direct thermal contact with a surface of an IC chip of a first IC package and a main non-conducting surface of the adjacent IC package. 7. The method of claim 1 , wherein said third IC package is an IC package including the PCB having two opposite main surfaces, each delimited by lateral edges, and lateral surfaces, each meeting each of the main surfaces at one of the lateral edges, the PCB comprising: a row of solder pads extending along a lateral edge of the PCB, with each solder pad of the row formed directly at said lateral edge and/or directly on one of the lateral surfaces meeting one of the two main surfaces at said lateral edge; and the integrated circuit chip, or IC chip, mounted on the PCB, a main surface of the IC chip facing and electrically connecting one of the two main surfaces of the PCB, the third IC package being soldered to said same hoard via the row of solder pads of the PCB of the third IC package, the row of solder pads formed directly at a lateral edge of the PCB of the third IC package and/or directly on a lateral surface of the PCB of the third IC package. 8. The method of claim 1 , wherein said thermally conducting layers are each thermally conducting foils. 9. The method of claim 1 , wherein the heat dissipating structure further comprises: a rigid structure in thermal communication with the thermally conducting layers, the latter being flexible foils, wherein each of the foils is bent so as for one portion of the foils to cover a main surface of the IC chip of one of the two neighboring IC packages, and a bent portion of the foils to be sandwiched between said lateral surface of the IC chip and said rigid structure. 10. The method of claim 1 , further comprising: electrically connecting the PCB of the third IC package to a PCB of one or each of said at least two IC packages via a flexible portion of one of the PCBs. 11. The method of claim 10 , wherein said flexible portion is folded around one of the thermally conducting layers.

Assignees

Inventors

Classifications

  • Folded back on itself · CPC title

  • Notches in edge pads · CPC title

  • One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence) · CPC title

  • Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers · CPC title

  • substantially perpendicularly to each other (H05K3/361 takes precedence) · CPC title

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Frequently asked questions

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What does patent US11096290B2 cover?
The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H05K3/403. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 17 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).