Error correction apparatus, operation method thereof and memory system using the same

Patent metadata

Field	Value
Publication number	US-11095310-B2
Application number	US-201916585564-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Dec 26, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.

First claim

What is claimed is:

1. An error correction apparatus comprising:
an input component configured to receive data;
an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability;
an error correction component configured to correct the errors of the received data based on the generated error information; and
an output component configured to output the corrected data,
wherein the error information generation component is configured to initiate an operation of generating second error information based on the second error detection ability simultaneously with an operation of generating first error information based on the first error detection ability or when the first error information is not generated based on the first error detection ability.

2. The error correction apparatus according to claim 1 , wherein the error information generation component comprises:
a first error information generation module configured to generate first error information as the error information by the first error detection ability;
a second error information generation module configured to generate second error information as the error information by the second error detection ability; and
an error information generation control module configured to control the operations of the first and second error information generation modules.

3. The error correction apparatus according to claim 2 , wherein when the first and second error information generation modules are operated in parallel to each other, the error information generation control module controls the second error information generation module to stop the operation of the second error information generation module, in the case that the first error information is generated by the first error information generation module and the second error information generation module is being operated.

4. The error correction apparatus according to claim 2 , wherein the error information generation component further comprises a syndrome computation module configured to perform a syndrome computation on the received data based on a parity check matrix,
wherein one or more of the first and second error information generation modules generate the error information based on the syndrome computation result.

5. The error correction apparatus according to claim 4 , wherein the error information generation component further comprises a polynomial generation module configured to generate a polynomial having the error information as roots based on the syndrome computation result,
wherein one or more of the first and second error information generation modules generate the error information based on the generated polynomial.

6. The error correction apparatus according to claim 5 , wherein the first error information generation module generates the first error information based on the number of a column vector of the parity check matrix, the column vector having a geometric ratio corresponding to a multiplying factor between the respective terms of the polynomial.

7. The error correction apparatus according to claim 6 , wherein the second error information generation module calculates the roots of the polynomial, and generates the second error information based on the calculated roots.

8. An error correction method comprising the steps of:
receiving data;
generating error information including the number of errors contained in the received data and the positions of the errors based on a first error detection ability to detect L errors, and generating the error information based on a second error detection ability to detect K errors, when the error information is not generated on the basis of the first error detection ability, where L is a positive integer and K is an integer larger than L;
correcting the errors of the received data based on the generated error information; and
outputting the corrected data,
wherein the generating of the error information includes generating first error information based on the first error detection ability and generating second error information based on the second error detection ability, and the generating of the second error information is initiated simultaneously with the generating of the first error information or when the first error information is not generated based on the first error detection ability.

9. The error correction method according to claim 8 , wherein in the step of generating the error information,
when L error detection abilities and K error detection abilities are applied in parallel, an operation for generating second error information through the K error detection abilities is stopped in the case that first error information is generated by the L error detection abilities and the operation for generating the second error information is being performed.

10. The error correction method according to claim 9 , wherein the step of generating the error information comprises the step of performing a syndrome computation on the received data based on a parity check matrix, and generating the error information by applying one or more of the L error detection abilities and the K error detection abilities to the syndrome computation result.

11. The error correction method according to claim 10 , wherein the step of generating the error information comprises the step of generating a polynomial having the error information as roots based on the syndrome computation result, and generating the error information by applying one or more of the L error detection abilities and the K error detection abilities to the generated polynomial.

12. The error correction method according to claim 11 , wherein the step of generating the error information by applying the L error detection abilities comprises the step of generating the error information based on the number of a column vector of the parity check matrix, the column vector having a geometric ratio corresponding to a multiplying factor between the respective terms of the polynomial.

13. The error correction method according to claim 12 , wherein the step of generating the error information by applying the K error detection abilities comprises the step of calculating the roots of the polynomial, and generating the error information based on the calculated roots.

14. A memory system comprising:
a memory device configured to store data therein according to a write command and output the data stored therein according to a read command; and
a controller configured to control the operation of the memory device,
wherein the controller comprises:
a memory interface configured to receive read data corresponding to a read request of a host from the memory device;
a data buffer configured to temporarily store the read data received through the memory interface and corrected data obtained by correcting the read data;
an error correction apparatus having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the read data sto

Assignees

• Sk Hynix Inc

Inventors

• Kim Dae Sung
• Shin Won Gyu

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03M13/1575 Primary

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• H03M13/1545

  Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial · CPC title