Time measurement circuit, system having a PWM signal generator circuit and a time measurement circuit, and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-11095291-B2
Application number	US-202017078945-A
Country	US
Kind code	B2
Filing date	Oct 23, 2020
Priority date	Oct 29, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.

First claim

The invention claimed is:

1. A time measurement circuit configured to generate a phase value, the time measurement circuit comprising:
a multiphase clock generator configured to generate a sequence of a given number n of phase shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction 1/n of said clock period, wherein one of said phase shifted clock phases represents a reference clock signal;
a node configured to receive an asynchronous event signal;
a phase sampling circuit configured to generate said phase value, said phase value being indicative of a number of said fractions 1/n of said clock period elapsed between an edge of said reference clock signal and an instant when said asynchronous event signal is set.

2. The time measurement circuit according to claim 1 , wherein said phase sampling circuit includes:
a first sub-circuit including for each of said phase shifted clock phases a respective first flip-flop configured to, in response to said asynchronous event signal, sample the respective phase shifted clock phase, thereby determining a respective first control signal indicating whether the respective clock phase was set to high or low at the instant when said asynchronous event signal was set;
a second sub-circuit including for each of said phase shifted clock phases a respective second flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective first control signal, thereby determining a respective second control signal corresponding to a synchronized version of the respective first control signal;
a third sub-circuit configured to:
associate with each of said phase shifted clock phases a further clock phase, said further clock phase corresponding to the phase shifted clock phase of said sequence of phase shifted clock phases preceding the respective clock phase with said time;
determine for each of said phase shifted clock phases a respective third control signal indicating whether:
the second control signal associated with the respective phase shifted clock phase indicates that the respective phase shifted clock phase was set to low at the instant when said asynchronous event signal was set, and
the second control signal associated with the respective further clock phase indicates that the respective further clock phase was set to high at the instant when said asynchronous event signal was set; and

a fourth sub-circuit including for each of said phase shifted clock phases a respective third flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective third control signal, thereby determining a respective fourth control signal corresponding to a synchronized version of the respective third control signal.

3. The time measurement circuit according to claim 2 , wherein:
each of said first flip-flops is configured to sample the respective phase shifted clock phase in response to a rising edge of said asynchronous event signal; and
each of said second flip-flops is configured to sample the respective first control signal in response to a falling edge of the respective phase shifted clock phase.

4. The time measurement circuit according to claim 2 , including for each of said phase shifted clock phases a respective logic OR gate configured to receive at input the respective first control signal provided by said respective first flip-flop and the respective second control signal provided by said respective second flip-flop, thereby determining a respective fifth control signal, and wherein each of said second flip-flops is configured to sample the respective fifth control signal, whereby each of said second flip-flops samples the respective first control signal only when the respective first control signal is set to high.

5. The time measurement circuit according to claim 2 , wherein said third sub-circuit includes for each of said phase shifted clock phases a respective logic AND gate, each logic AND gate configured to receive at input an inverted version of the second control signal associated with the respective phase shifted clock phase, and the second control signal associated with the respective further clock phase, thereby generating the respective third control signal.

6. The time measurement circuit according to claim 2 , wherein:
each of said third flip-flops is configured to sample the respective third control signal in response to a rising edge of the respective phase shifted clock phase.

7. The time measurement circuit according to claim 2 , wherein said first, second and third flip-flops are configured to be reset via a reset signal.

8. The time measurement circuit according to claim 2 , wherein a further flip-flop is connected in cascade with each of said second or said third flip-flops.

9. The time measurement circuit according to claim 2 , wherein said fourth control signals represents a one-hot encoding of said phase value.

10. The time measurement circuit according to claim 2 , wherein said reference clock signal is selected among said phase shifted clock phases as a function of a selection signal, and wherein said phase value is determined as a function of said fourth control signals and said selection signal.

11. The time measurement circuit according to claim 1 , comprising:
a counter circuit configured to increase a count value in response to said reference clock signal; and
a counter sampling circuit configured to generate a sampled count value by sampling said count value.

12. The time measurement circuit according to claim 11 , wherein said counter sampling circuit comprises:
a first sampling circuit configured to, in response to a rising edge of said reference clock signal, sample said asynchronous event signal, thereby generating a first synchronized asynchronous event signal;
a second sampling circuit configured to, in response to a falling edge of said reference clock signal, sample said asynchronous event signal, thereby generating a second synchronized asynchronous event signal; and
a sampling circuit configured to, in response to a rising edge of said reference clock signal, store either the count value of said counter circuit or the count value of said counter circuit decreased by one as a function of said first and said second synchronized asynchronous event signal, thereby generating said sampled count value.

13. A system, comprising:
a time measurement circuit, including:
a multiphase clock generator configured to generate a sequence of a given number n of phase shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction 1/n of said clock period, wherein one of said phase shifted clock phases represents a reference clock signal;
a node configured to receive an asynchronous event signal;
a phase sampling circuit configured to generate a phase value, said phase value being indicative of a number of said fractions 1/n of said clock period elapsed between an edge of said reference clock signal and an instant when said asynchronous event signal is set;
a counter circuit configured to increase a count value in response to said reference clock signal; and
a counter sampling circuit configured to generate a sampled count value by sampling said count value; and
a Pulse-Width Modulated (PWM) signal generator circuit configured to generate a Pulse Width Modulated signal as a function of the count value of said counter circuit,
wherein said sampled count value and said phase value are indicative of a number of clock cycles and the fractions 1/n of said reference clock signal elapsed between an edge of said Pulse-Wid

Assignees

• St Microelectronics Srl

Inventors

• Tripodi Domenico

Classifications

• G04F10/04 Primary

  by counting pulses or half-cycles of an AC {(G04F10/005 takes precedence)} · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03L7/24

  using a reference signal directly applied to the generator · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• G04F10/00

  Apparatus for measuring unknown time intervals by electric means · CPC title