Bonded nanofluidic device chip stacks

Patent metadata

Field	Value
Publication number	US-11094683-B2
Application number	US-201916364649-A
Country	US
Kind code	B2
Filing date	Mar 26, 2019
Priority date	Mar 26, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

First claim

What is claimed is:

1. A method of forming a bonded chip stack, the method comprising: forming a first nanofluidic device chip having a first through-wafer via;
forming a second nanofluidic device chip having a second through-wafer via;
washing the first nanofluidic device chip and the second nanofluidic device chip with a detergent solution;
activating a first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip by treating the first surface and the second surface with an activation solution;
arranging the first nanofluidic device chip and the second nanofluidic device chip in a stack, wherein the first through-wafer via is aligned with the second through wafer via in a substantially straight line; and
subjecting the stack of first and second nanofluidic device chips to annealing conditions.

2. The method of claim 1 further comprising depositing a glass coverslip or a silicon cap layer on top of the stack of the nanofluidic device chips.

3. The method of claim 1 , wherein the washing is carried out by subjecting the nanofluidic device chips to the detergent solution at its boiling point for a period of 20 to 30 minutes.

4. The method of claim 3 , wherein the detergent solution comprises an about 1% volume/volume aqueous detergent solution.

5. The method of claim 4 , wherein the detergent is selected from a group consisting of non-ionic polyethyleneoxide polymers and derivatives, ionic detergents, electronics grade surfactants, and mixtures thereof.

6. The method of claim 1 , wherein the activation solution is selected from a group consisting of:
1:1 volume/volume solution of sulfuric acid and 30% (v/v) hydrogen peroxide; and
oxygen or ozone plasma or a rapid wash with a strong alkaline solution.

7. The method of claim 6 , wherein the activating comprises subjecting the nanofluidic device chips to the activation solution at a temperature of about 80° C. to about 100° C. for about 40 to about 80 minutes.

8. The method of claim 1 , wherein:
the arranging is carried out in an alignment jig comprising at least three walls; and
the alignment jig has alignment accuracy of about 50 to about 100 μm.

9. The method of claim 8 , wherein the arranging comprises sequentially depositing the nanofluidic device chips into a mechanical pocket formed by walls of the alignment jigs.

10. The method of claim 9 further comprising applying a pressure of about 100-500 psi to the stack after addition of each of the first and second nanofluidic device chips.

11. The method of claim 1 further comprising depositing a glass coverslip or a silicon cap on top of the stack prior to subjecting the stack to the annealing conditions.

12. The method of claim 11 , wherein:
the stack comprises the glass coverslip; and
the annealing conditions comprise a maximum annealing temperature of about 550° C. to 600° C.

13. The method of claim 11 , wherein:
the stack comprises the silicon cap; and
the annealing conditions comprise a maximum annealing temperature of about 600-1000° C.

14. The method of claim 1 , wherein the annealing is carried out in an annealing box comprising a material having coefficient of thermal expansion less than that of silicon.

15. The method of claim 14 , wherein the annealing box comprises a material selected from a group consisting of invar metal, invar alloy, alloy, ceramic material having low coefficient of thermal expansion, and combinations thereof.

16. A method of producing a bonded chip stack, the method comprising:
providing at least two nanofluidic device chips wherein each nanofluidic device chip comprises at least one through wafer via;
forming a silicon oxide layer on the surface of each of the at least two nanofluidic device chips;
implanting a boron layer on the silicon oxide layer;
washing the nanofluidic device chips with a detergent solution;
arranging the nanofluidic device chips in a stack wherein the at least one through wafer via of each nanofluidic device chip is aligned in a straight line;
applying an electrical voltage to the stack of nanofluidic device chips.

17. The method of claim 16 further comprising subjecting the stack of first and second nanofluidic device chips to annealing conditions.

18. The method of claim 16 further comprising heating the stack of first and second nanofluidic device chips to a temperature of about 350° C. to about 450° C. prior to applying the electric voltage.

19. The method of claim 16 , wherein the electric voltage comprises 100-500 volt direct current, and the voltage is applied for a period of 40 to 90 minutes.

Assignees

• IBM

Inventors

• Wunsch Benjamin
• Smith Joshua T
• Gifford Stacey
• Pereira Michael Albert

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title

• H10W72/0711

  Apparatus therefor · CPC title