Semiconductor device and manufacturing method

Patent metadata

Field	Value
Publication number	US-11094553-B2
Application number	US-201816485702-A
Country	US
Kind code	B2
Filing date	Feb 22, 2018
Priority date	Mar 8, 2017
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

The present technology relates to a semiconductor device and a manufacturing method that make it possible to reduce PID. The semiconductor device includes a first layer, a second layer laminated with the first layer, a conductive member that comes into contact with a lateral surface of a groove part formed in the first layer and the second layer, and first wiring that is formed in the second layer and comes into contact with a bottom surface of the groove part. The conductive member is connected to a protecting element for discharging charges accumulated inside the groove part. The present technology is applicable to, for example, the formation of a via in a silicon substrate and an interlayer film laminated with each other.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first layer;
a second layer laminated with the first layer;
a groove part in the first layer and the second layer, wherein the groove part is configured to accumulate charges inside the groove part;
a conductive member outside the groove part, wherein the conductive member is in contact with a lateral surface of the groove part;
first wiring in the second layer, wherein the first wiring is in contact with a bottommost surface of the groove part;
second wiring in the second layer, wherein the second wiring is below the bottommost surface of the groove part; and
a first protecting element connected to the conductive member via the second wiring, wherein the first protecting element is configured to discharge the charges accumulated inside the groove part.

2. The semiconductor device according to claim 1 , wherein
the first layer is a semiconductor layer, and
the groove part is a via that penetrates the semiconductor layer.

3. The semiconductor device according to claim 2 , wherein
the conductive member is one of a contact, a gate electrode, or third wiring.

4. The semiconductor device according to claim 3 , wherein
the first protecting element is one of a ground or a diode, and
the ground is connected to the semiconductor layer.

5. The semiconductor device according to claim 4 , wherein
the conductive member and the first wiring are electrically separated from each other.

6. The semiconductor device according to claim 5 , wherein the conductive member comes into contact with the lateral surface of the via at a position closer to a processing surface than a position at which the first wiring comes into contact with the bottommost surface of the via.

7. The semiconductor device according to claim 5 , wherein
the conductive member is formed so as to surround a periphery of the lateral surface of the via or formed so as to come into contact with a part of the lateral surface of the via.

8. The semiconductor device according to claim 5 , wherein
the lateral surface of the via is covered with an insulating film and covers the conductive member.

9. The semiconductor device according to claim 5 , wherein
the conductive member is connected to a forward diode serving as the first protecting element, and
the forward diode is a diode having an N-type substrate or an N-type well and having a P-type surface injection layer.

10. The semiconductor device according to claim 5 , wherein
the conductive member is connected to a reverse diode serving as the first protecting element, and
the reverse diode is a diode having a P-type substrate and an N-type surface injection layer.

11. The semiconductor device according to claim 5 , wherein
the conductive member is the gate electrode, and
the gate electrode at least partially includes an injection layer made of a prescribed injection ion species or a metal layer made of a prescribed metal material.

12. The semiconductor device according to claim 1 , further comprising a circuit that includes a transistor and a second protecting element, wherein
the second protecting element protects the transistor,
the first layer is a silicon substrate,
the second layer is an interlayer film,
the first wiring is in the interlayer film, and
the first wiring is connected to the circuit.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Miyake Shinichi

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title