Rearranging columns and rows of two-dimensional image pixel data

Patent metadata

Field	Value
Publication number	US-11094284-B2
Application number	US-201816623968-A
Country	US
Kind code	B2
Filing date	Jun 26, 2018
Priority date	Jul 10, 2017
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

An image processing device and image processing method that reduce the probability that the power consumption of two processing systems will be maximized simultaneously. Such image processing device includes an image processing circuit, a conversion circuit receiving a first pixel data array outputted from the image processing circuit and converting the first pixel data array into a second pixel data array by converting an arrangement of pieces of pixel data included in the first pixel data array pixel by pixel, the first pixel data array being an aggregate of a plurality of pieces of pixel data, the pieces of pixel data being pieces of data corresponding to a plurality of pixels, each of the pieces of pixel data having a plurality of bits, an aggregate of the pixels forming a pixel array, and a processing unit processing the second pixel data array outputted from the conversion circuit.

First claim

The invention claimed is:

1. A image processing device comprising:
a first image processing circuit;
a first conversion circuit configured to receive a first pixel data array outputted from the first image processing circuit and to convert the first pixel data array into a second pixel data array by converting an arrangement of pieces of pixel data included in the first pixel data array pixel by pixel,
the first and the second pixel data array each being an aggregate of a plurality of pieces of pixel data,
the pieces of pixel data being data corresponding to pieces of pixels, the pixel data comprising a plurality of bits,
an aggregate of the pixels forming a pixel array;

a second image processing circuit configured to perform, on the second pixel data array outputted from the first conversion circuit, image processing that does not depend on positional relationships among pieces of pixel data in the second pixel data array; and
a second conversion circuit configured to receive the second pixel data array processed by the second image processing circuit and to reconvert the second pixel data array into the first pixel data array, wherein
the pixel array is a two-dimensional array comprising M×N pixels, M satisfying M≥2, N satisfying N≥2, and
the first conversion circuit is configured to perform the converting by processing M pieces of pixel data in parallel N times, the M pieces of pixel data being column data,
the first conversion circuit is configured to convert, being independent to pixel arrangements of the first pixel data array, the first pixel data array into the second pixel data array by transposing a square matrix of p rows and p columns that is all or part of the first pixel data array, p satisfying p≤M and p≤N,
the square matrix has a plurality of matrix elements each corresponding to the pixel data of the first pixel data array,
in the transposing the square matrix, each of the matrix elements in row i and column j is swapped to a position in row j and column i, i and j satisfying 0≤i≤p, and 0≤j≤p.

2. The image processing device of claim 1 , wherein M=N is satisfied.

3. An image processing method comprising:
a first image processing step;
a first conversion step of converting a first pixel data array outputted in the first image processing step into a second pixel data array by converting an arrangement of pieces of pixel data included in the first pixel data array pixel by pixel,
the first and the second pixel data array each being an aggregate of a plurality of pieces of pixel data,
the pieces of pixel data being data corresponding to pieces of pixels, the pixel data comprising a plurality of bits,
an aggregate of the pixels forming a pixel array;

a second processing step of performing, on the second pixel data array outputted from the first conversion step, image processing that does not depend on positional relationships among pieces of pixel data in the second pixel data array; and
a second conversion step of receiving the second pixel data array processed in the second processing step and reconverting the second pixel data array into the first pixel data array, wherein
the pixel array is a two-dimensional array comprising M×N pixels, M satisfying M≥2, N satisfying N≥2, and
the converting in the first conversion step comprises
processing M pieces of pixel data in parallel N times, the M pieces of pixel data being column data,
converting, being independent to pixel arrangements of the first pixel data array, the first pixel data array into the second pixel data array by transposing a square matrix of p rows and p columns that is all or part of the first pixel data array, p satisfying p≤M and p≤N,

the square matrix has a plurality of matrix elements each corresponding to the pixel data of the first pixel data array,
in the transposing the square matrix, each of the matrix elements in row i and column j is swapped to a position in row j and column i, i and j satisfying 0≤i≤p, and 0≤j≤p.

4. A image processing device comprising:
an image processing circuit;
a first conversion circuit configured to receive a first pixel data array outputted from the image processing circuit and to convert the first pixel data array into a second pixel data array by converting an arrangement of pieces of pixel data included in the first pixel data array pixel by pixel,
the first and the second pixel data array each being an aggregate of a plurality of pieces of pixel data,
the pieces of pixel data being data corresponding to pieces of pixels, the pixel data comprising a plurality of bits,
an aggregate of the pixels forming a pixel array;

a processing unit configured to process the second pixel data array outputted from the first conversion circuit; and
a second conversion circuit configured to receive the second pixel data array processed by the processing unit and to reconvert the second pixel data array into the first pixel data array, wherein
the pixel array is a two-dimensional array comprising M×N pixels, M satisfying M≥2, N satisfying N≥2, and
the first conversion circuit is configured to perform the converting by processing M pieces of pixel data in parallel N times, the M pieces of pixel data being column data,
the first conversion circuit is configured to convert, being independent to pixel arrangements of the first pixel data array, the first pixel data array into the second pixel data array by transposing a square matrix of p rows and p columns that is all or part of the first pixel data array, p satisfying p≤M and p≤N,
the square matrix has a plurality of matrix elements each corresponding to the pixel data of the first pixel data array,
in the transposing the square matrix, each of the matrix elements in row i and column j is swapped to a position in row j and column i, i and j satisfying 0≤i≤p, and 0≤j≤p.

Assignees

• Eizo Corp

Inventors

• Matsuzaki Hiroki
• Yamamoto Masato
• Nakamae Takashi
• Ito Tsubasa

Classifications

• G09G5/001 Primary

  Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor · CPC title

• G09G2352/00

  Parallel handling of streams of display data · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title