Coding for avoiding motion artifacts

Patent metadata

Field	Value
Publication number	US-11094251-B2
Application number	US-201916722672-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 21, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method includes representing dots of an image to be displayed within a field by a digital image code. The field is divided into sub-fields which are further divided into a first and second time interval which respectively comprise a first and a second number of equally long time slots. Time slots are assigned to each bit of the digital image code according to each bit's significance. Successive time slots of the first time interval are assigned to one of the bits of the image code and successive time slots of the second time interval are assigned to a different one of the bits of the image code. Within the duration of at least one sub-field, each rows is selected twice for respectively writing a first bit of the image code during the first time interval and writing a second bit of the image code during the second time interval.

First claim

What is claimed is:

1. A method for reducing motion artifacts in moving image sequences displayed on a digitally driven active-matrix display comprising a plurality of display pixels logically organized in a plurality of rows and a plurality of columns, the method comprising:
representing each of a plurality of dots of an image to be displayed within a field by an n-bit digital image code, n being greater than 4,
dividing the field into a plurality of sequential, time-ordered sub-fields equal in duration, each sub-field being further divided into a first time interval and a second time interval respectively comprising a first number and a second number of equally long time slots,
assigning a number of time slots to each bit of the n-bit digital image code according to each bit's significance in the digital image code, such that, for each but one sub-field, successive time slots of the first time interval are assigned to one of the bits of the digital image code, to be written during the first time interval of the sub-field, and successive time slots of the second time interval are assigned to a different one of the bits of the digital image code, to be written during the second time interval of the sub-field,
within a duration of at least one sub-field, sequentially selecting each of the plurality of rows twice, wherein upon a first selection a first bit of the digital image code is written to the selected row during the first time interval and upon a second selection a second bit of the digital image code, different from the written first bit of the digital image code, is written to the selected row during the second time interval, there being a predetermined time delay between moments of first and second selection,
wherein the plurality of sub-fields consists of a first group of sub-fields and a second group of sub-fields, wherein a most significant bit of the digital image code is present in each subfield of the first group of sub-fields and not present in any subfield of the second group of sub-fields, the plurality of sub-fields being arranged chronologically such that a total number of sub-fields of the second group that are consecutive in time is minimized.

2. The method according to claim 1 , wherein the most significant bit and a second most significant bit of the digital image code are each written during time intervals which are substantially regularly distributed over the sub-fields comprised in one field.

3. The method according to claim 2 , wherein the most significant bit, the second most significant bit and a third most significant bit of the digital image code are each written during time intervals which are substantially regularly distributed over the sub-fields comprised in one field.

4. The method according to claim 1 , wherein the most significant bit of the digital image code is written during time intervals associated with more than 50% of the sub-fields comprised in one field.

5. The method according to claim 1 , wherein the delay between the first selection and the second selection in the at least one sub-field is equal or less than the delay between the first selection and the second selection in any further subsequent sub-field.

6. The method according to claim 1 , wherein a number of sub-fields comprised in one field equals a power of two.

7. The method according to claim 1 , wherein each sub-field comprises an equal number of time slots.

8. The method according to claim 1 , wherein the second number of time slots in a second time interval of at least one sub-field is zero and only one bit of the digital image code is written during the at least one sub-field.

9. The method according to claim 1 , wherein writing the bit of the digital image code during the first interval and writing the second bit of the digital image code during the second interval comprises driving the bits using pulse-width modulation.

10. A digital driver circuitry for driving display pixels of an active-matrix display arranged in rows and columns, the digital driver circuitry comprising
a digital row select driver for sequentially selecting each one of a plurality of rows for each sub-field in a plurality of sub-fields of equal duration comprised in a field to be displayed at a first time and for sequentially selecting each one of a plurality of rows for at least one sub-field at a second time, there being a delay between a first selection of a row at the first time and a second selection of that same row at the second time, wherein the plurality of sub-fields consists of a first group of sub-fields and a second group of sub-fields,
a digital column data driver for writing bits of an n-bit digital image code to corresponding display pixels of a selected row, a first bit of the digital image code being written during a first interval upon a first selection of a row and a second bit of the digital image code, different from the written first bit, being written upon a second selection of that same row, n being greater than 4, and
a controller for synchronizing the digital row select driver and the digital column data driver, the controller being adapted for generating the first bit of the digital image code to be written within each sub-field or generating the first bit and second bit of the digital image code to be written within the at least one sub-field of the field, such that a most significant bit of the digital image code is present in each subfield of the first group of sub-fields and not present in any subfield of the second group of sub-fields, the plurality of sub-fields being arranged chronologically such that a total number of sub-fields of the second group that are consecutive in time is minimized.

11. The digital driver circuitry according to claim 10 , wherein the digital row select driver comprises at least two shift registers or at least two linear arrays of clocked flip-flops.

12. An active-matrix display comprising a plurality of display pixels arranged in rows and columns, a plurality of row bitlines and data bitlines, each display pixel being connected to one of the row bitlines and one of the data bitlines, wherein the active-matrix display further comprises a digital driver circuitry according to claim 10 , the digital driver circuitry being connected to the each of the plurality of row bitlines and each of the plurality of data bitlines.

13. The method of claim 4 , wherein a second most significant bit of the digital image code is written during time intervals associated with at least 25% of the sub-fields comprised in one field.

14. The digital driver circuitry according to claim 10 , wherein the most significant bit and a second most significant bit of the digital image code are each written during time intervals which are substantially regularly distributed over the sub-fields comprised in one field.

15. The digital driver circuitry according to claim 14 , wherein the most significant bit, the second most significant bit and a third most significant bit of the digital image code are each written during time intervals which are substantially regularly distributed over the sub-fields comprised in one field.

16. The digital driver circuitry according to claim 10 , wherein the most significant bit of the digital image code is written during time intervals associated with more than 50% of the sub-fields comprised in one field.

17. The digital driver circuitry according to claim 10 , wherein the delay between the first selection and the second selection in the at least one sub-field is equal or less than the delay between the first selection and the second selection in a

Assignees

• Imec Vzw

Inventors

• Genoe Jan

Classifications

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/2025 Primary

  the sub-frames having all the same time duration · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0271

  Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title