Write out stage generated bounding volumes

Patent metadata

Field	Value
Publication number	US-11094102-B2
Application number	US-202016797125-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Apr 1, 2017
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.

First claim

What is claimed is:

1. A system comprising:
a memory including one or more write out buffers; and
a graphics pipeline apparatus comprising one or more processors and a write out fixed-function stage, implemented at least partly in electronic circuitry, to
receive geometry data for one or more objects, and
generate, based on the geometry data, one or more bounding volumes as inputs to one or more graphics processing stages, and
write processed vertex data from the one or more graphics processing stages to the one or more write out buffers according to the bounding volumes;

wherein the write out fixed-function stage is triggered to write the one or more bounding volumes into the one or more write out buffers in response to at least a bounding volume N-dimensional state being changed from an enabled state to a disabled state, wherein N is an integer equal to 3 or 4, and
wherein when the graphics pipeline apparatus comprises a plurality of processors, the graphics pipeline apparatus includes one or more communication paths between the processors, the one or more communication paths consisting essentially of one or more of an interconnect fabric, a high-speed bus or a point-to-point interconnect.

2. The system of claim 1 , wherein the write out fixed-function stage is to generate the one or more bounding volumes without host processor synchronization.

3. The system of claim 2 , wherein the one or more bounding volumes include bounding volumes of a three-dimensional (3D) object.

4. The system of claim 3 , wherein the write out fixed-function stage writes a portion of transformed 3D vertices into the one or more write out buffers.

5. The system of claim 4 , wherein the write out fixed-function stage is to calculate or output the one or more bounding volumes for each patch of a tessellated draw for a tessellated draw call.

6. The system of claim 5 , wherein the one or more bounding volumes are to be written consecutively into the one or more write out buffers, and wherein each of the bounding volumes are defined by a minimum bounds and a maximum bounds for each dimension of an N dimensional bounding volume.

7. The system of claim 1 , wherein the one or more bounding volumes based on the geometry data are used as inputs to the one or more graphics processing stages to perform one or more of sorting objects, intersection detections or other graphics processing.

8. The system of claim 1 , further comprising a display subsystem communicatively coupled to the graphics pipeline apparatus, wherein the display subsystem is to visually present one or more scenes associated with the bounding volumes.

9. The system of claim 8 , further comprising a power source to supply power to the system.

10. A method comprising:
receiving, by a write out fixed-function stage of a graphics pipeline apparatus, geometry data for one or more objects, the graphics pipeline apparatus comprising one or more processors;
generating, by the write out fixed-function stage, based on the geometry data, one or more bounding volumes as inputs to one or more stages of the graphics pipeline apparatus; and
writing out, by the write out fixed-function stage, processed vertex data from the one or more stages of the graphics pipeline apparatus to one or more write out buffers according to the bounding volumes,
wherein the write out fixed-function stage is triggered to write the one or more bounding volumes into the one or more write out buffers in response to at least a bounding volume N-dimensional state being changed from an enabled state to a disabled state, wherein N is an integer equal to 3 or 4, and
wherein when the graphics pipeline apparatus comprises a plurality of processors, the graphics pipeline apparatus includes one or more communication paths between the processors, the one or more communication paths consisting essentially of one or more of an interconnect fabric, a high-speed bus or a point-to-point interconnect.

11. The method of claim 10 , wherein the one or more bounding volumes are generated without host processor synchronization.

12. The method of claim 11 , wherein the one or more bounding volumes include bounding volumes of a three-dimensional (3D) object.

13. The method of claim 12 , further comprising writing a portion of transformed 3D vertices into the one or more write out buffers of a memory.

14. The method of claim 13 , further comprising:
calculating or outputting the one or more bounding volumes for each patch of a tessellated draw for a tessellated draw call.

15. The method of claim 14 , wherein each of the bounding volumes is defined by a minimum bounds and a maximum bounds for each dimension of an N dimensional bounding volume.

16. The method of claim 10 , wherein the one or more bounding volumes based on the geometry data are used as inputs to the one or more stages of the graphics pipeline apparatus to perform one or more of sorting objects, intersection detections or other graphics processing.

17. At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a computing device, cause the computing device to:
receive, by a write out fixed-function stage of a graphics pipeline apparatus, geometry data for one or more objects, the graphics pipeline apparatus comprising one or more processors;
generate, by the write out fixed-function stage, based on the geometry data, one or more bounding volumes as inputs to one or more stages of the graphics pipeline apparatus; and
write out, by the write out fixed-function stage, processed vertex data from the one or more stages of the graphics pipeline apparatus to one or more write out buffers according to the bounding volumes,
wherein the write out fixed-function stage is triggered to write the one or more bounding volumes into the one or more write out buffers in response to at least a bounding volume N-dimensional state being changed from an enabled state to a disabled state, wherein N is an integer equal to 3 or 4, and
wherein when the graphics pipeline apparatus comprises a plurality of processors, the graphics pipeline apparatus includes one or more communication paths between the processors, the one or more communication paths consisting essentially of one or more of an interconnect fabric, a high-speed bus or a point-to-point interconnect.

18. The at least one non-transitory computer readable storage medium of claim 17 , wherein the one or more bounding volumes are generated without host processor synchronization.

19. The at least one non-transitory computer readable storage medium of claim 18 , wherein the one or more bounding volumes include bounding volumes of a three-dimensional (3D) object.

20. The at least one non-transitory computer readable storage medium of claim 19 , wherein the instructions, when executed, further cause the computing system to write a portion of transformed 3D vertices into the one or more write out buffers of a memory.

21. The at least one non-transitory computer readable storage medium of claim 20 , wherein the instructions, when executed, further cause the computing system to calculate or output the one or more bounding volumes for each patch of a tessellated draw for a tessellated draw call.

22. The at least one non-transitory computer readable storage medium of claim 21 , wherein each of the bounding volumes is defined by a minimum bounds and a maximum bounds for each dimension of an N dimensional bounding volume.

23. The at le

Assignees

• Intel Corp

Inventors

• Doyle Peter L

Classifications

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06T2210/12

  Bounding box · CPC title

• G06F9/384

  Register renaming · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title