System and method for early DRAM page-activation

Patent metadata

Field	Value
Publication number	US-11093393-B2
Application number	US-201916289650-A
Country	US
Kind code	B2
Filing date	Feb 28, 2019
Priority date	Dec 27, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

First claim

What is claimed is:

1. A system, comprising:
a memory controller;
an interconnect coupled to the memory controller; and
a processor coupled to the memory controller through a first path and a second path, the first path being through the interconnect and the second path bypassing the interconnect, the processor sending a first memory access request to the memory controller via the first path and receiving at least one response corresponding to the first memory access request from the memory controller via the first path, the processor sending concurrently a second memory access request to the memory controller via the first path and a page activation request to the memory controller via the second path, and the processor receiving a first feedback message via the second path in response to the page activation request sent via the second path that regulates a number of page activation requests that are sent by the processor.

2. The system of claim 1 , wherein the processor further dynamically determines whether to send a third memory access request via the second path based on a type of the third memory access request or a current power or performance state of the system.

3. The system of claim 1 , further comprising a memory coupled to the memory controller,
wherein the processor sends the page activation request via the second path, the page activation request including a page address, and
wherein the memory controller determines whether a page of the memory corresponding to the second memory access request is already open, and activates a page of the memory associated with the page address prior to accessing the memory in response to the second memory access request based on the memory controller determining that the page of the memory corresponding to the second memory access request is not already open.

4. The system of claim 1 , further comprising a memory coupled to the memory controller,
wherein the processor sends the page activation request via the second path, the page activation request including a page address, and
wherein the memory controller ignores the page activation request prior to accessing the memory in response to the second memory access request.

5. The system of claim 1 , wherein the memory controller sends the first feedback message to the processor.

6. A computing system, comprising:
a processor;
a coherent interconnect coupled to the processor; and
a memory controller coupled to the processor through a first path and a second path, the first path being through the coherent interconnect and the second path bypassing the coherent interconnect, the memory controller receiving a first memory access request from the processor via the first path and sending a response to the first memory access request to the processor via the first path, the memory controller receiving a second memory access request from the processor via the first path and receiving a page activation request via the second path, the second memory access request received via the first path and the page activation request received via the second path being sent concurrently by the processor,
the processor receiving a first feedback message via the second path in response to the page activation request sent via the second path that regulates a number of page activation requests that are sent by the processor.

7. The computing system of claim 6 , wherein the memory controller further dynamically determines whether to respond to the second memory access request via the second path based on a type of the second memory access request or a current power/performance state of the computing system.

8. The computing system of claim 6 , wherein the memory controller receives the page activation request via the second path, the page activation request including a page address, and
wherein the memory controller further determines whether a page of a memory corresponding to the second memory access request is already open, and
activates a page of a memory associated with the page address prior to accessing the memory in response to the second memory access request based on the memory controller determining that the page of the memory corresponding to the second memory access request is not already open.

9. The computing system of claim 6 , wherein the memory controller receives the page activation request via the second path, the page activation request including a page address, and
wherein the memory controller further ignores the page activation request prior to accessing a memory in response to the second memory access request.

10. The computing system of claim 6 , wherein the memory controller sends the first feedback message to the processor.

11. A method to access a memory, comprising:
receiving at a memory controller a page activation request over a first path that was sent to the memory controller concurrently with a memory access request over a second path, the first path bypassing an interconnect connected to the memory controller and the second path being through the interconnect, the page activation request including a page address; and
activating, by the memory controller, a page of the memory corresponding to the page address in response to the page activation request prior to accessing the memory in response to the memory access request based on the memory controller determining that the page of the memory corresponding to the page activation request is not already open;
responding, by the memory controller, to the memory access request by sending data corresponding to the memory access request over the second path; and
sending by the memory controller via the first path a feedback message in response to the page activation request received over the first path that regulates a number of page activation requests that are sent to the memory controller.

12. The method of claim 11 , further comprising dynamically determining by the memory controller whether to respond to the memory access request via the second path based on a type of the memory access request or a current power or performance state of the memory controller.

13. The method of claim 11 , further comprising ignoring by the memory controller the page activation request based on the memory controller determining that the page activation request is to be ignored.

14. The method of claim 11 , wherein the page activation request was sent by a processor.

15. The system of claim 1 , wherein the interconnect sends a second feedback message to the processor.

16. The computing system of claim 6 , wherein coherent interconnect sends a second feedback message to the processor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Le Hien
• Yoo Junhee
• Sinha Vikas Kumar
• Bell Robert
• Garrett Matthew Derrick

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title