Display panel and manufacturing method thereof, driving method and display device

Patent metadata

Field	Value
Publication number	US-11092866-B2
Application number	US-201916631331-A
Country	US
Kind code	B2
Filing date	Jul 18, 2019
Priority date	Jul 19, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

The present disclosure provides a display panel and a manufacturing method thereof, a driving method and a display device. The display panel includes: a base substrate and a thin film transistor on a surface of the base substrate. The thin film transistor includes: a gate, and a source and a drain arranged along a first direction, and a first passivation layer covering the gate, the source and the drain. a space region in which liquid crystal molecules are filled is formed in the first passivation layer. The space region is between the source and the drain. The source and the drain are configured to control rotation of the liquid crystal molecules.

First claim

What is claimed is:

1. A display panel, comprising: a base substrate and a thin film transistor on the base substrate, the thin film transistor comprising: a gate, and a source and a drain arranged along a first direction, and a first passivation layer covering the gate, the source and the drain; wherein
the first passivation layer is provided with a space region in which liquid crystal molecules are filled;
the space region is between the source and the drain; and
the source and the drain are configured to control rotation of the liquid crystal molecules, wherein
the first passivation layer is further provided a hole through which the liquid crystal molecules are filled into the space region,
the display panel further comprises:
a second passivation layer on a side of the first passivation layer distal to the base substrate and seals the hole; and
a planarization layer on a side of the second passivation layer distal to the base substrate.

2. The display panel according to claim 1 , wherein
the gate is on the base substrate;
the thin film transistor further comprises an insulating layer and an active layer,
the insulating layer is on a side of the gate distal to the base substrate and covers the gate and the base substrate; and
the active layer is on a side of the insulating layer distal to the base substrate.

3. The display panel according to claim 2 , wherein
the source and the drain extend from a first edge to a second edge of the active layer and onto the insulating layer along a second direction crossing the first direction, the second edge being opposite to the first edge, and
the space region is at least between portions of the source and the drain beyond the second edge of the active layer.

4. The display panel according to claim 3 , further comprising a color filter on a side of the planarization layer distal to the base substrate, wherein
the color filter comprises a color resist layer and a black matrix layer;
an orthographic projection of the color resist layer on the base substrate is overlapped with an orthographic projection of the space region between the portions on the base substrate; and
the black matrix layer is between adjacent color resist layers to separate the adjacent color resist layers.

5. The display panel according to claim 4 , further comprising: a third passivation layer; wherein
the third passivation layer is on a side of the color filter distal to the base substrate.

6. The display panel according to claim 1 , wherein
a distance from a highest point of the space region to a surface of the base substrate is less than a distance from a highest point of the source and the drain to the surface of the base substrate.

7. The display panel according to claim 1 , wherein
a distance between the source and the drain ranges from about 10 nm to 50 μm, and
each of the source and the drain has a height in a range of about 10 nm to 20 μm.

8. A display device, comprising: the display panel according to claim 1 , a backlight module, a first polarizer and a second polarizer.

9. A method for manufacturing a display panel, comprising:
providing a base substrate;
forming a gate, and a source and a drain arranged along a first direction on the base substrate;
forming a first passivation layer covering the gate, the source and the drain, wherein a space region is disposed in the first passivation layer; and
filling the space region with liquid crystal molecules, wherein
the space region is between the source and the drain; and
the source and the drain are configured to control rotation of the liquid crystal molecules,
the step of filling the space region with the liquid crystal molecules comprises:
forming a hole in communication with the space region in the first passivation layer; and
filling the space region with the liquid crystal molecules through the hole,
the method further comprises:
forming a second passivation layer sealing the hole on a side of the first passivation layer distal to the base substrate; and
forming a planarization layer on a side of the second passivation layer distal to the base substrate.

10. The method according to claim 9 , wherein the step of forming the gate, and the source and the drain arranged along the first direction on the base substrate comprises:
forming a gate on the base substrate;
forming an insulating layer on a side of the gate distal to the base substrate, the insulating layer covering the gate and the base substrate;
forming an active layer on a side of the insulating layer distal to the base substrate; and
forming the source and the drain on a side of the active layer distal to the base substrate.

11. The method according to claim 10 , wherein the step of forming the source and the drain on the side of the active layer distal to the base substrate comprises:
forming the source and the drain such that the source and the drain extend from a first edge to a second edge of the active layer and onto the insulating layer along a second direction crossing the first direction, the second direction being opposite to the first edge, wherein
the space region is at least between portions of the source and the drain beyond the second edge of the active layer.

12. The method according to claim 11 , wherein the step of forming the source and the drain on the side of the active layer distal to the base substrate further comprises:
forming the source and the drain such that:
a distance between the source and the drain ranges from about 10 nm to 50 μm, and
each of the source and the drain has a height in a range of about 10 nm to 20 μm.

13. The method according to claim 11 , further comprising: forming a color filter on a side of the planarization layer distal to the base substrate, wherein
the color filter comprises a color resist layer and a black matrix layer;
an orthographic projection of the color resist layer on the base substrate is overlapped with an orthographic projection of the space region between the portions on the base substrate; and
the black matrix layer is between adjacent color resist layers to separate the adjacent color resist layers.

14. The method according to claim 13 , further comprising
forming a third passivation layer on a side of the color filter distal to the base substrate.

15. The method according to claim 9 , wherein
a distance from a highest point of the space region to a surface of the base substrate is less than a distance from a highest point of the source and the drain to the surface of the base substrate.

16. A method for driving a display panel wherein the display panel comprises: a base substrate and a thin film transistor on the base substrate, the thin film transistor comprising: a gate, a source and a drain arranged along a first direction, and a first passivation layer covering the gate, the source and the drain,
the first passivation layer is provided with a space region in which liquid crystal molecules are filled,
the space region is between the source and the drain,
the source and the drain are configured to control rotation of the liquid crystal molecules,
the first passivation layer is further provided a hole through which the liquid crystal molecules are filled into the space region,
the display panel further comprises:
a second passivation layer on a side of the first passivation layer distal to the base substrate and seals the holes; and
a planarization layer on a side of the second passivation layer distal to the base substrate,
the method comprises:
applying a driving voltage to the gate of the thin film transis

Assignees

• Boe Technology Group Co Ltd

Inventors

• Hu hehe
• Ma Xiaochen
• Yuan Guangcai
• Ning ce
• Gu Xin

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• G02F1/136222

  Colour filters incorporated in the active matrix substrate · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title