Temperature protection circuit

Patent metadata

Field	Value
Publication number	US-11092497-B2
Application number	US-201916458585-A
Country	US
Kind code	B2
Filing date	Jul 1, 2019
Priority date	Oct 31, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.

First claim

What is claimed is:

1. A circuit, comprising:
a temperature-sensitive voltage divider, comprising:
a temperature-sensitive resistor; and
a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor, wherein a temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor; and

detection logic coupled to the first node to generate a detection signal responsive to the temperature signal.

2. The circuit of claim 1 , wherein the detection logic comprises a first inverter to generate the detection signal, the detection signal changing from a first logic state to a second logic state responsive to the temperature signal having a voltage associated with an over-temperature condition.

3. The circuit of claim 2 , wherein the first inverter comprises a differential amplifier comprising a first input terminal coupled to the first node and a second input terminal coupled to a reference voltage, and the differential amplifier changes the detection signal from the first logic state to the second logic state responsive to the voltage of the temperature signal exceeding the reference voltage by a first margin.

4. The circuit of claim 3 , wherein the differential amplifier changes the detection signal from the second logic state to the first logic state responsive to the reference voltage exceeding the voltage of the temperature signal by a second margin.

5. The circuit of claim 3 , wherein the differential amplifier comprises:
a first input transistor, wherein the first input terminal is coupled to a gate of the first input transistor;
a second input transistor, wherein the second input terminal is coupled to a gate of the second input transistor;
a first load transistor comprising a first source/drain coupled to a first source/drain of the first input transistor; and
a second load transistor comprising a first source/drain coupled to a first source/drain of the second input transistor.

6. The circuit of claim 5 , wherein a gate of the first load transistor and a gate of the second load transistor are coupled to the first source/drain of the second load transistor.

7. The circuit of claim 5 , wherein the differential amplifier comprises a bias transistor comprising a first source/drain coupled to a second source/drain of the first input transistor and a second source/drain of the second input transistor.

8. The circuit of claim 1 , wherein the temperature-sensitive resistor comprises an electron gas resistor.

9. A circuit, comprising:
a temperature-sensitive voltage divider, comprising:
a temperature-sensitive resistor;
a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor; and
a third resistor having a first terminal coupled to a second terminal of the second resistor;

an active device having a first source/drain coupled to the first terminal of the third resistor, a second source/drain coupled to a second terminal of the third resistor, and a gate coupled to a node between the first terminal of the temperature-sensitive resistor and the first terminal of the second resistor; and
a logic device controllably gated based on a voltage at the node.

10. The circuit of claim 9 , comprising:
a first inverter having an input terminal coupled to the node and an output terminal coupled to the gate of the active device, wherein the gate of the active device is coupled to the node through the first inverter.

11. The circuit of claim 10 , comprising:
a second inverter having an input terminal coupled to the output terminal of the first inverter and the gate of the active device.

12. The circuit of claim 11 , wherein the second inverter has an output terminal coupled to an input terminal of the logic device.

13. The circuit of claim 10 , wherein the input terminal of the first inverter, the first terminal of the temperature-sensitive resistor and the first terminal of the second resistor are commonly coupled to the node.

14. The circuit of claim 9 , wherein the second terminal of the second resistor, the first terminal of the third resistor, and the first source/drain of the active device are commonly coupled.

15. The circuit of claim 9 , wherein at least one of:
the second resistor comprises at least one of silicon or chromium, or
the third resistor comprises at least one of silicon or chromium.

16. A method, comprising:
changing a resistance of a temperature-sensitive resistor based on a change in temperature of a circuit comprising the temperature-sensitive resistor;
changing an operating state of an active device comprised within the circuit based on changing of the resistance of the temperature-sensitive resistor; and
controlling a load comprised within the circuit based on changing of the operating state of the active device.

17. The method of claim 16 , wherein changing the operating state of the active device comprises:
logically inverting a signal generated at a first terminal of the temperature-sensitive resistor to generate an inverted signal; and
applying the inverted signal to a gate of the active device.

18. The method of claim 17 , wherein controlling the load comprises:
logically inverting the inverted signal to generate a second signal; and
applying the second signal to enable logic connected to the load.

19. The method of claim 16 , comprising employing a hysteresis when changing the operating state of the active device.

20. The method of claim 16 , comprising disabling the load for a predetermined period of time after changing the operating state of the active device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chern Chan-Hong
• Chen Kun-Lung
• Tsai Ming Hsien

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• G01K7/183 Primary

  characterised by the use of the resistive element · CPC title

• G01K7/25

  for modifying the output characteristic, e.g. linearising · CPC title

• G01R19/0092

  Measuring current only · CPC title