Low noise power supply MOSFET gate drive scheme

Patent metadata

Field	Value
Publication number	US-11088609-B2
Application number	US-201414542231-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A switching power supply can include multiple power MOSFETs that receive an initial gate drive waveform comprising a fast slew rate region having a negative slope and a slow slew rate region also having a negative slope. The MOSFETs can turn off during the slow slew rate region of the initial gate drive waveform.

First claim

What is claimed is:

1. A method of controlling a metal-oxide-semiconductor field-effect transistor (MOSFET) in a switching power supply, the method comprising:
in a single on-to-off transition of the transistor, applying a voltage waveform to a gate of the transistor, the voltage waveform having a steeper slope in a first stage of the voltage waveform and a more shallow slope in a second stage of the voltage waveform;
determining that the transistor has turned off at the conclusion of the single on-to-off transition;
determining which of the first stage or the second stage of the voltage waveform was being applied to the gate of the transistor when the transistor turned off; and
adjusting a starting voltage value of the voltage waveform to be applied to the gate of the transistor in a subsequent on-to-off transition to cause the transistor to turn off at the conclusion of the subsequent on-to-off transition while the second stage of the voltage waveform is being applied to the gate of the transistor.

2. The method of claim 1 , in which the voltage waveform applied to the gate of the transistor has an unchanging shape for each on-to-off transition of the transistor.

3. The method of claim 1 , in which, as compared between the first stage of the voltage waveform and the second stage of the voltage waveform, the transistor turns off more quickly while the first stage of the voltage waveform is applied to the gate of the transistor; and in which the transistor turns off more slowly while the second stage of the voltage waveform is applied to the gate of the transistor.

4. The method of claim 1 , in which, as compared between the first stage of the voltage waveform and the second stage of the voltage waveform, the transistor power supply generates more common mode electrical noise when the transistor turns off while the first stage of the voltage waveform is being applied to the gate of the transistor.

5. The method of claim 1 , in which the transistor is an NMOS transistor, and in which the voltage waveform applied to the gate of the transistor is decreasing in voltage value in the first stage and the second stage.

6. The method of claim 1 , in which the transistor is an NMOS transistor, and in which the starting voltage value of the voltage waveform is a positive voltage.

7. The method of claim 1 , in which the transistor is an NMOS transistor, and in which the starting voltage value of the voltage waveform is above the actual threshold voltage of the transistor.

8. The method of claim 1 , in which the transistor is an NMOS transistor, and in which adjusting the starting voltage value comprises increasing the starting voltage value.

9. The method of claim 8 , in which the starting voltage value is increased from approximately 2.3 volts to 3.7 volts.

10. The method of claim 1 , in which the transistor is an NMOS transistor, and in which increasing the starting voltage value causes the transistor to be turned off at a point nearer to an end of the second stage of the voltage waveform than nearer to a beginning of the first stage of the voltage waveform.

11. The method of claim 1 , in which the transistor is a PMOS transistor, and in which the voltage waveform applied to the gate of the transistor is increasing in voltage value in the first stage and the second stage.

12. The method of claim 1 , in which the transistor is a PMOS transistor, and in which the starting voltage value of the voltage waveform is a negative voltage.

13. The method of claim 1 , in which the transistor is a PMOS transistor, and in which the starting voltage value of the voltage waveform is below the actual threshold voltage of the transistor.

14. The method of claim 1 , in which the transistor is a PMOS transistor, and in which adjusting the starting voltage value of the voltage waveform comprises decreasing the starting voltage value.

15. The method of claim 1 , in which the transistor is a PMOS transistor, and in which decreasing the starting voltage value causes the transistor to be turned off at a point nearer to an end of the second stage of the voltage waveform than nearer to a beginning of the first stage of the voltage waveform.

16. The method of claim 1 , in which the voltage waveform applied to the gate of the transistor comprises, in a single off-to-on transition of the transistor:
a third stage having an equal but opposite slope compared to the second stage of the gate driving waveform; and
a fourth stage having an equal but opposite slope compared to the first stage of the gate driving waveform.

17. The method of claim 1 , in which determining that the transistor has turned off comprises inspecting a voltage at a drain of the transistor.

18. The method of claim 1 , in which determining that the transistor has turned off comprises comparing a voltage at a drain of the transistor to a voltage where it is known that the transistor is on.

19. A driving circuit for a gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) in a switching power supply, the driving circuit comprising:
a defined voltage waveform for applying to a gate of the transistor in a single on-to-off transition of the transistor, the voltage waveform having a steeper slope in a first stage of the voltage waveform and a more shallow slope in a second stage of the voltage waveform;
a detection component structured to determine when the transistor has turned off at the end of the on-to-off transition;
a stage comparator structured to determine which of the first stage or the second stage of the voltage waveform was being applied to the gate of the transistor when the transistor turned off; and
a tuning circuit structured to adjust a starting voltage value of the voltage waveform to be applied to the gate of the transistor in a subsequent on-to-off transition to cause the transistor to turn off while the second stage of the voltage waveform is being applied to the gate of the transistor during the subsequent on-to-off transition.

20. The driving circuit of claim 19 , in which the defined voltage waveform applied to the gate of the transistor has an unchanging shape for each on-to-off transition of the transistor.

21. The driving circuit of claim 19 , in which the transistor is an NMOS transistor, and in which the voltage waveform applied to the gate of the transistor is decreasing in voltage value in the first stage and the second stage.

22. The method of claim 21 , in which the transistor is an NMOS transistor, and in which the starting voltage value of the voltage waveform is a positive voltage.

23. The driving circuit of claim 19 , in which the transistor is an NMOS transistor, and in which the tuning circuit is structured to adjust the starting voltage value by increasing the starting voltage value.

24. The driving circuit of claim 19 , in which the defined voltage waveform for applying to the gate of the transistor comprises:
a third stage having an equal but opposite slope compared to the second stage of the gate driving waveform; and
a fourth stage having an equal but opposite slope compared to the first stage of the gate driving waveform.

25. The driving circuit of claim 19 , in which the detection component comprises a voltage comparator structured to compare a voltage at a drain of the transistor to a voltage where it is known that the transistor is on.

26. A push-pull switching power supply, comprising:
a first transistor coupl

Assignees

• Keithley Instruments

Inventors

• Goeke Wayne C

Classifications

• H03K17/163 Primary

  Soft switching · CPC title

• H02M1/0029

  Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate · CPC title

• H03K17/166

  Soft switching · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H03K2217/0036

  Means reducing energy consumption · CPC title