Through-silicon-via fabrication in planar quantum devices

Patent metadata

Field	Value
Publication number	US-11088310-B2
Application number	US-201916396992-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	Apr 29, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).

First claim

What is claimed is:

1. A method comprising:
patterning, on a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator;
patterning, on a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator, wherein the first surface and the second surface are disposed relative to each other in a non-co-planar disposition;
creating, in the substrate, a recess, the recess extending from the first superconducting layer to the second superconducting layer;
depositing, on an inner surface of the recess, a third superconducting layer, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer;
removing, from the first surface and the second surface, forming a completed through-silicon via (TSV), excess material of the third superconducting layer.

2. The method of claim 1 , further comprising:
depositing, on the patterned first surface, a first protective layer;
depositing on the patterned second surface, a second protective layer; and
performing the creating such that the recess extends from the first protective layer to the second protective layer.

3. The method of claim 2 , wherein the first protective layer comprises an oxide layer.

4. The method of claim 2 , further comprising:
etching, within a substrate portion of the recess, an undercut region, wherein a diameter of the undercut region is greater than a diameter of the recess at the first superconducting layer.

5. The method of claim 4 , wherein the etching is performed using an isotropic silicon dry etch process.

6. The method of claim 4 , further comprising:
depositing, on the second protective layer prior to creating the recess, an etch stop layer; and
removing, from the second protective layer after etching the undercut region, the etch stop layer.

7. The method of claim 6 , wherein the etch stop layer comprises a silicon nitride layer.

8. The method of claim 2 , further comprising:
further depositing the third superconducting layer on the first protective layer and the second protective layer.

9. The method of claim 8 , further comprising:
further removing the third superconducting layer from the first protective layer and the second protective layer.

10. The method of claim 2 , further comprising:
further removing, from the first patterned surface and the second patterned surface, the first protective layer and the second protective layer.

11. The method of claim 10 , further comprising:
etching, prior to removing the first protective layer and the second protective layer, a portion of the third superconducting layer, the portion occupying the recess in the protective layer.

12. The method of claim 1 , wherein each of the first superconducting layer, the second superconducting layer, and the third superconducting layer, comprises a titanium nitride layer.

13. The method of claim 1 , wherein the removing uses an etching process.

14. The method of claim 1 , wherein the completed TSV is a hollow superconductor.

15. The method of claim 1 , wherein the first component of the resonator is an inductive element, and wherein the inductive element and a qubit are disposed on the same surface.

16. The method of claim 1 , wherein the first component of the resonator is a capacitive element, and wherein the capacitive element and a qubit are disposed on the same surface.

17. The method of claim 1 , wherein the first component of the resonator is a conductive pad, wherein the conductive pad and a qubit are disposed on the same surface, and wherein an inductive element and a capacitive element of the resonator are disposed on the opposite surface.

Assignees

• IBM

Inventors

• Rubin Joshua M
• Hertzberg Jared Barney
• Rosenblatt Sami
• Adiga Vivekananda P
• Brink Markus
• Kumar Arvind

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/4484

  Superconducting materials · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title