Oxide semiconductor field effect transistor and forming method thereof

Patent metadata

Field	Value
Publication number	US-11088285-B2
Application number	US-201816154644-A
Country	US
Kind code	B2
Filing date	Oct 8, 2018
Priority date	Sep 7, 2018
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

First claim

What is claimed is:

1. An oxide semiconductor field effect transistor, comprising:
a first insulating layer disposed on a substrate;
a source and a drain disposed in the first insulating layer;
only a U-shaped channel layer sandwiched by the source and the drain without having any channel layers under the source and the drain;
a metal gate disposed on the U-shaped channel layer, wherein the metal gate comprises a gate oxide layer and a metal layer, and the U-shaped channel layer comprises a plurality of oxide semiconductor layers; and
a composite layer located between the gate oxide layer and the metal layer.

2. The oxide semiconductor field effect transistor according to claim 1 , wherein the metal gate comprises a low resistivity metal.

3. The oxide semiconductor field effect transistor according to claim 2 , wherein the gate oxide layer and the metal layer have U-shaped cross-sectional profiles.

4. The oxide semiconductor field effect transistor according to claim 1 , wherein a top surface of the metal gate is higher than top surfaces of the source and the drain.

5. The oxide semiconductor field effect transistor according to claim 1 , wherein a top surface of the U-shaped channel layer is higher than top surfaces of the source and the drain.

6. The oxide semiconductor field effect transistor according to claim 1 , further comprising:
an insulating layer disposed between the first insulating layer and the substrate.

7. The oxide semiconductor field effect transistor according to claim 6 , further comprising:
a back gate insulating layer disposed between the first insulating layer and the insulating layer.

8. The oxide semiconductor field effect transistor according to claim 6 , further comprising:
a back gate disposed right below the U-shaped channel layer and in the insulating layer.

9. The oxide semiconductor field effect transistor according to claim 8 , wherein the whole U-shaped channel layer vertically overlaps the back gate.

10. The oxide semiconductor field effect transistor according to claim 9 , wherein the back gate protrudes from the U-shaped channel layer.

11. The oxide semiconductor field effect transistor according to claim 1 , further comprising:
a cap layer conformally covering the source and the drain, and the first insulating layer blanketly covering the cap layer.

Assignees

• United Microelectronics Corp

Inventors

• Lai Chien-Ming
• Chen Yen-Chen
• Huang Jen-Po
• Huang sheng-yao
• Chen Hui-Ling
• Xing Qinggang
• Chen Ding-Lung
• Ding Li Li
• Liu Yao-Hung

Classifications

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title