Pin diode including a conductive layer, and fabrication process

Patent metadata

Field	Value
Publication number	US-11088241-B2
Application number	US-202016739753-A
Country	US
Kind code	B2
Filing date	Jan 10, 2020
Priority date	Jan 16, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

First claim

The invention claimed is:

1. A diode, comprising:
a polycrystalline silicon bar including a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region that is located between the first doped region and the second doped region;
a first conductive layer extending parallel to the polycrystalline silicon bar; and
a dielectric layer separating the first conductive layer from said polycrystalline silicon bar, wherein the dielectric layer includes a first portion positioned between the intrinsic region and the first conductive layer and a second portion positioned between each of the first and second doped regions and the first conductive layer, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness;
wherein said first conductive layer is configured to be biased by a bias voltage.

2. The diode according to claim 1 , wherein a thickness of the polycrystalline silicon bar is 150 nm or 100 nm.

3. The diode according to claim 1 , wherein each of the first and second doped regions of the polycrystalline silicon bar have a third thickness and the intrinsic region the polycrystalline silicon bar has a fourth thickness greater than the third thickness.

4. The diode according to claim 1 , wherein a part of the second portion is positioned between a part of the intrinsic region and the first conductive layer.

5. The diode according to claim 1 , wherein the first thickness of the first portion is substantially 2.3 nm.

6. The diode according to claim 1 , wherein the first thickness of the first portion is between 7 nm and 9 nm.

7. The diode according to claim 1 , wherein second thickness of the second portion is substantially 15 nm.

8. The diode according to claim 1 , wherein the second thickness of the second portion is substantially 18 nm.

9. The diode according to claim 1 , wherein said first conductive layer is located on a surface on a front face of a semiconductor substrate.

10. The diode according to claim 9 , wherein the front face is defined by a shallow trench isolation region in the semiconductor substrate.

11. The diode according to claim 1 , wherein said first conductive layer is located in a trench extending vertically into a semiconductor substrate from a front face of the semiconductor substrate.

12. The diode according to claim 11 , further comprising an insulating layer lining said trench to isolate the first conductive layer from the semiconductor substrate.

13. The diode according to claim 1 , further comprising an electrical circuit coupling the first doped region of the polycrystalline silicon bar with the first conductive layer.

14. The diode according to claim 1 , further comprising:
a second conductive layer extending parallel to the polycrystalline silicon bar;
a second dielectric layer separating the second conductive layer from said polycrystalline silicon bar;
wherein said second conductive layer is configured to be biased by a second bias voltage.

15. The diode according to claim 14 , wherein the first conductive layer is located on one side of the polycrystalline silicon bar and the second conductive layer is located on an opposite side of the polycrystalline silicon bar.

16. The diode according to claim 14 , wherein a thickness of the second conductive layer is 150 nm and a thickness of the polycrystalline silicon bar is 100 nm.

17. The diode according to claim 14 , wherein said second dielectric layer includes a first portion and a second portion, wherein the first portion is thinner than the second portion, and wherein the first portion is positioned between the intrinsic region and the second conductive layer.

18. The diode according to claim 17 , wherein a thickness of said first portion of the second dielectric layer is substantially 2.3 nm and a thickness of the second portion of the second dielectric layer is substantially 15 nm.

19. The diode according to claim 14 , further comprising a second electrical circuit coupling the first doped region of the polycrystalline silicon bar with the second conductive layer.

20. The diode according to claim 1 , further including an isolating region electrically isolating the diode from a semiconductor substrate.

21. The diode according to claim 1 , wherein at least said intrinsic region of the polycrystalline silicon bar includes fluorine atoms.

22. A diode, comprising:
a substrate support;
a first conductive layer in contact with the substrate support and extending parallel to an upper surface of the substrate support;
a dielectric layer in contact with the first conductive layer and extending parallel to an upper surface of the first conductive layer;
wherein the dielectric layer includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness; and
a polycrystalline silicon bar in contact with the dielectric layer and extending parallel to an upper surface of the dielectric layer;
wherein the polycrystalline silicon bar includes a first doped region with a first conductivity type separated from the conductive layer by the first portion of the dielectric layer, a second doped region with a second conductivity type separated from the conductive layer by the first portion of the dielectric layer and an intrinsic region that is located between the first doped region and the second doped region separated from the conductive layer by the second portion of the dielectric layer.

23. The diode according to claim 22 , wherein said first conductive layer is configured to be biased by a first bias voltage.

24. The diode according to claim 22 , wherein a thickness of the polycrystalline silicon bar is from 100-150 nm.

25. The diode according to claim 1 , wherein a part of the second portion is positioned between a part of the intrinsic region and the first conductive layer.

26. The diode according to claim 1 , wherein the first thickness of the first portion is from 2-9 nm and the second thickness of the second portion is from 15-18 nm.

27. The diode according to claim 22 , wherein said substrate support is a surface on a front face of a semiconductor substrate.

28. The diode according to claim 27 , wherein the front face is defined by a shallow trench isolation region in the semiconductor substrate.

29. The diode according to claim 22 , wherein said substrate support is a trench within a semiconductor substrate.

30. The diode according to claim 29 , further comprising an insulating layer lining said trench to isolate the first conductive layer from the semiconductor substrate.

31. The diode according to claim 22 , further comprising an electrical circuit coupling the first doped region of the polycrystalline silicon bar with the first conductive layer.

32. The diode according to claim 22 , further comprising:
a second conductive layer extending parallel to the polycrystalline silicon bar; and
a second dielectric layer separating the second conductive layer from said polycrystalline silicon bar.

33. The diode according to claim 32 , wherein said first conductive layer is configured to be biased by a first bias voltage and wherein said second conductive layer is configured to be biased by a second bi

Assignees

• St Microelectronics Rousset

Inventors

• Fornara Pascal

Classifications

• H10D48/381

  Multistable devices; Devices having two or more distinct operating states · CPC title

• H10D8/50 Primary

  PIN diodes · CPC title

• H10D8/01

  Manufacture or treatment · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6737

  characterised by the electrode materials · CPC title