Semiconductor devices including upper and lower selectors

Patent metadata

Field	Value
Publication number	US-11088163-B2
Application number	US-201916527506-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Mar 19, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lower stack structure including an alternating stack of a plurality of lower word lines and a plurality of lower insulating layers;
a plurality of lower channel structures configured to extend through the lower stack structure;
an upper stack structure on the lower stack structure, the upper stack structure including an alternating stack of a plurality of upper word lines and a plurality of upper insulating layers;
a plurality of upper channel structures isolated from direct contact with the plurality of lower channel structures, the plurality of upper channel structures configured to extend through the upper stack structure;
a decoder adjacent to the lower stack structure and the upper stack structure;
a plurality of signal interconnections connected to the decoder;
a plurality of lower selectors connected to the plurality of lower word lines; and
a plurality of upper selectors connected to the plurality of upper word lines,
wherein each of the plurality of signal interconnections is connected to
a separate, respective lower selector of the plurality of lower selectors, and
a separate, respective upper selector of the plurality of upper selectors.

2. The semiconductor device of claim 1 , wherein each of the plurality of signal interconnections is connected to
a separate, respective lower word line of the plurality of lower word lines via the separate, respective lower selector of the plurality of lower selectors, and
a separate, respective upper word line of the plurality of upper word lines via the separate, respective upper selector of the plurality of upper selectors.

3. The semiconductor device of claim 1 , wherein
the plurality of lower selectors includes
a lower selection line,
a plurality of lower selection channel structures disposed adjacent to the lower selection line,
a plurality of first electrodes between the plurality of lower selection channel structures and the plurality of lower word lines, and
a plurality of second electrodes disposed between the plurality of lower selection channel structures and the plurality of signal interconnections, and the plurality of upper selectors includes
an upper selection line isolated from direct contact with the lower selection line,
a plurality of upper selection channel structures adjacent to the upper selection line,
a plurality of third electrodes between the plurality of upper selection channel structures and the plurality of upper word lines, and
a plurality of fourth electrodes between the plurality of upper selection channel structures and the plurality of signal interconnections.

4. The semiconductor device of claim 3 , wherein
each lower selection channel structure of the plurality of lower selection channel structures extends through the lower selection line, and
each upper selection channel structure of the plurality of upper selection channel structures extends through the upper selection line.

5. The semiconductor device of claim 4 , wherein each selection channel structure of the plurality of lower selection channel structures and the plurality of upper selection channel structures includes
a channel layer; and
a gate dielectric layer configured to surround an outer longitudinal surface of the channel layer.

6. The semiconductor device of claim 5 , wherein
the channel layer is connected to the plurality of first electrodes and the plurality of second electrodes, or
the channel layer is connected to the plurality of third electrodes and the plurality of fourth electrodes.

7. The semiconductor device of claim 5 , wherein
each of the plurality of lower selection channel structures and the plurality of upper selection channel structures further includes a core layer, and
the channel layer surrounds an outer longitudinal surface of the core layer.

8. The semiconductor device of claim 7 , wherein
each of the plurality of lower selection channel structures and the plurality of upper selection channel structures further includes a selection pad, and
the selection pad is
between the channel layer and the plurality of second electrodes, or
between the channel layer and the plurality of fourth electrodes.

9. The semiconductor device of claim 3 , wherein the upper selection line and the lower selection line are coplanar with each other.

10. The semiconductor device of claim 1 , further comprising:
a plurality of lower bit lines connected to separate, respective lower channel structures of the plurality of lower channel structures; and
a plurality of upper bit lines connected to separate, respective upper channel structures of the plurality of upper channel structures.

11. The semiconductor device of claim 10 , wherein the plurality of lower bit lines and the plurality of upper bit lines are adjacent to each other between the lower stack structure and the upper stack structure.

12. The semiconductor device of claim 11 , wherein the plurality of upper bit lines are isolated from direct contact with the plurality of lower bit lines.

13. The semiconductor device of claim 11 , further comprising:
a plurality of upper string selection lines between the plurality of upper bit lines and the plurality of upper word lines.

14. The semiconductor device of claim 11 , further comprising:
an upper ground selection line on the plurality of upper word lines.

15. A semiconductor device, comprising:
a lower stack structure including an alternating stack of a plurality of lower word lines and a plurality of lower insulating layers;
a plurality of lower channel structures configured to extend through the lower stack structure;
an upper stack structure on the lower stack structure, the upper stack structure including an alternating stack of a plurality of upper word lines and a plurality of upper insulating layers;
a plurality of upper channel structures isolated from direct contact with the plurality of lower channel structures, the plurality of upper channel structures configured to extend through the upper stack structure;
a decoder adjacent to the lower stack structure and the upper stack structure;
a signal interconnection connected to the decoder;
a lower selector connected to the signal interconnection and further connected to one of the plurality of lower word lines; and
an upper selector isolated from direct contact with the lower selector, connected to the signal interconnection, and further connected to one of the plurality of upper word lines.

16. A semiconductor device, comprising:
a lower stack structure including a lower word line;
an upper stack structure on the lower stack structure, the upper stack structure including an upper word line;
a decoder adjacent to the lower stack structure and the upper stack structure;
a signal interconnection connected to the decoder;
a lower selector connected to the signal interconnection and connected to the lower word line; and
an upper selector connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line,
wherein each of the lower selector and the upper selector includes one or more transistors.

17. The semiconductor device of claim 16 , wherein
each of the lower selector and the upper selector includes a plurality of vertical transistors, and
at least one pair of the plurality of vertical transistors, are connected in parallel.

18. The semiconductor device of claim 16 , further comprising:
a lower channel structure configured to extend

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kanamori Kohji
• Kim Yong Seok
• Lee Kyung Hwan
• Lim Jun Hee
• Han Jee Hoon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title