Effective medium semiconductor cavities for RF applications

Patent metadata

Field	Value
Publication number	US-11088097-B2
Application number	US-201916414042-A
Country	US
Kind code	B2
Filing date	May 16, 2019
Priority date	Dec 31, 2015
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An electronic package apparatus is formed from a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.

First claim

The invention claimed is:

1. An electronic package apparatus comprising:
a semiconductor substrate comprising a cavity extending entirely through the semiconductor substrate, wherein the cavity comprises a horizontal topmost plane, a horizontal bottommost plane, and is bound by vertical sidewall surfaces of two vertical spacers extending only from the horizontal bottommost plane of the cavity to the horizontal topmost plane of the cavity, wherein the horizontal bottommost plane of the cavity is open and the two vertical spacers comprise a dielectric material;
a dielectric layer directly on an entire topmost horizontal surface of the semiconductor substrate, wherein the dielectric layer spans across the entire horizontal topmost plane of the cavity and an entire horizontal topmost surface of each of the two vertical spacers; and
at least one metal via contact located in the dielectric layer, wherein the at least one metal via contact has a bottommost surface that is coplanar with the horizontal topmost plane of the cavity and the at least one metal via contact is positioned over the cavity.

2. The electronic package apparatus of claim 1 , wherein at least one of the two vertical spacers has a lateral dimension of less than 0.1 mm.

3. The electronic package apparatus of claim 1 , wherein the semiconductor substrate comprises silicon.

4. The electronic package apparatus of claim 1 , wherein at least one of the two vertical spacers is a U-shaped spacer.

5. The electronic package apparatus of claim 4 , wherein the at least one U-shaped spacer comprises a void between vertical sidewalls of the U-shaped spacer.

6. The electronic package apparatus of claim 1 , wherein the two vertical spacers are parallel spacers.

7. The electronic package apparatus of claim 6 , wherein each of the two parallel spacers is U-shaped.

8. The electronic package apparatus of claim 7 , further comprising a void between vertical sidewalls of at least one of the two parallel, U-shaped spacers.

9. The electronic package apparatus of claim 1 , wherein the cavity comprises a void.

10. The electronic package apparatus of claim 1 , wherein the topmost horizontal surface of the semiconductor substrate is coplanar with the topmost horizontal surface of at least one of the two vertical spacers.

11. The electronic package apparatus of claim 1 , wherein the horizontal topmost plane of the cavity is coplanar with the topmost horizontal surface of at least one of the two vertical spacers.

12. The electronic package apparatus of claim 11 , wherein the horizontal bottommost plane of the cavity is coplanar with a bottommost horizontal surface of at least one of the two vertical spacers.

13. The electronic package apparatus of claim 1 , wherein the horizontal bottommost plane of the cavity is bound by a dielectric material.

14. The electronic package apparatus of claim 1 , further comprising a transparent layer directly on a topmost horizontal surface of the dielectric layer.

15. The electronic package apparatus of claim 1 , further comprising a metal strip structure embedded in the dielectric layer.

16. The electronic package apparatus of claim 1 , further comprising another dielectric layer directly on a bottommost horizontal surface of the semiconductor substrate.

17. An electronic package apparatus comprising:
a semiconductor substrate comprising a plurality of cavities extending entirely through the semiconductor substrate, wherein each cavity of the plurality cavities comprises a horizontal topmost plane, a horizontal bottommost plane, and is bound by vertical sidewall surfaces of two vertical spacers extending only from the horizontal bottommost plane of each cavity of the plurality cavities to the horizontal topmost plane of each cavity of the plurality cavities, wherein the two vertical spacers comprise a dielectric material;
a first dielectric layer directly on an entire topmost horizontal surface of the semiconductor substrate, wherein the first dielectric layer spans across the entire horizontal topmost plane of each cavity of the plurality of cavities and an entire horizontal topmost surface of each of the two vertical spacers;
a second dielectric layer along an entire bottommost horizontal surface of the semiconductor substrate;
an antenna located within the second dielectric layer and spanning across the entire horizontal bottommost plane of a first cavity of the plurality of cavities and along a bottommost surface of both of the two vertical spacers that bound the first cavity of the plurality of cavities wherein the horizontal bottommost plane of a second cavity of the plurality of cavities is opened, and at least one metal via contact is located in the first dielectric layer, wherein the at least one metal via contact has a bottommost surface that is coplanar with the horizontal topmost plane of the second cavity and the at least one metal via contact is positioned over the second cavity.

Assignees

• IBM

Inventors

• Webb Bucknell C

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20 Primary

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H01Q9/065

  Microstrip dipole antennas (patch antenna H01Q9/0407) · CPC title

• H01Q1/2283

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title