Subpixel circuitry for driving an associated light element, and method, display system and electronic device relating to same

US11087674B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11087674-B2
Application numberUS-201816486026-A
CountryUS
Kind codeB2
Filing dateFeb 1, 2018
Priority dateFeb 14, 2017
Publication dateAug 10, 2021
Grant dateAug 10, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal V P to provide a digital control signal V C relating to a digital data signal V D , the digital periodic signal V P defining 2 N +1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal V D has a predetermined value at a predetermined one of the 2 N +1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.

First claim

Opening claim text (preview).

The invention claimed is: 1. A subpixel circuit comprising: a first switching device configured to: receive a digital periodic signal, the digital periodic signal defining 2 N +1 time slots within each frame cycle, where N is a predetermined integer; receive a digital data signal, the digital data signal comprising a sequence of binary logic states of “0” and “1”, and having a predetermined state at a predetermined one of the 2 N +1 time slots; and provide a digital control signal from the digital data signal, based on the digital periodic signal; and a second switching device responsive to the digital control signal to drive an associated light emitting element, wherein an average luminance level of light emitted by the associated light emitting element during a frame cycle is proportional to a number of time slots within the frame cycle at which the digital data signal has the logic state of “1”. 2. The subpixel circuit of claim 1 , wherein the predetermined time slot is one of the first and last time slots. 3. The subpixel circuit of claim 1 , wherein: the first switching device includes a first terminal adapted to receive the digital data signal, a second terminal for providing the digital control signal, and a control terminal adapted to receive the digital periodic digital signal; and the second switching device includes a first terminal adapted to receive a supply voltage, a second terminal adapted to be connected electrically to a light emitting element, and a control terminal connected electrically to the second terminal of the first switching device. 4. The subpixel circuit of claim 1 , comprising no capacitive element electrically connected between the switching devices. 5. The subpixel circuit of claim 4 , comprising no capacitive element. 6. The subpixel circuit of claim 1 , wherein each of the switching devices includes a transistor. 7. The subpixel circuit of claim 6 , wherein each of the switching devices is configured to normally operate in a linear region thereof. 8. A display system comprising: a plurality of light emitting elements; a plurality of subpixel circuits of claim 1 operatively associated with the light emitting elements; a coder unit operatively associated with the subpixel circuits and responsive to a first input signal to provide the digital data signal; and a selection unit operatively associated with the subpixel circuits and responsive to a second input signal to provide the digital periodic signal. 9. The display system of claim 8 , wherein each of the first and second input signal is a digital input signal. 10. The display system of claim 8 , wherein the light emitting elements include organic light emitting diodes (OLED). 11. An electronic device comprising: a display system of claim 8 ; and a graphics processing unit operatively associated with the coder unit and the selection unit and configured to generate the first and second input signals. 12. The electronic device of claim 11 , wherein the display system comprises an OLED display. 13. A control method for a subpixel circuit, comprising driving an associated light emitting element in response to a digital control signal, the digital control signal being related to a digital data signal and derived from a digital periodic signal, the digital periodic signal defining 2 N +1 time slots within each frame cycle, where N is a predetermined integer, the digital data signal comprises a sequence of binary logic states of “0” and “1”, and having a predetermined state at a predetermined one of the 2 N +1 time slots, wherein an average luminance level of light emitted by the associated light emitting element during a frame cycle is proportional to a number of time slots within the frame cycle at which the digital data signal has the logic state of “1”. 14. The control method of claim 13 , wherein the predetermined time slot is one of the first and last time slots.

Assignees

Inventors

Classifications

  • by time modulation using two or more time intervals · CPC title

  • Several active elements per pixel in active matrix panels · CPC title

  • being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements · CPC title

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • the sub-frames having all the same time duration · CPC title

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What does patent US11087674B2 cover?
Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal V P to provide a digital control signal V C relating to a digital data signal V D , the digital periodic signal V P defining 2 N +1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal V D has a predetermined value at a predeterm…
Who is the assignee on this patent?
Univ Nanyang Tech, Massachusetts Inst Technology, Nat Univ Singapore
What technology area does this patent fall under?
Primary CPC classification G09G3/3225. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 10 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).