Platform environment control interface tunneling via enhanced serial peripheral interface

Patent metadata

Field	Value
Publication number	US-11086812-B2
Application number	US-201514998222-A
Country	US
Kind code	B2
Filing date	Dec 26, 2015
Priority date	Dec 26, 2015
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

First claim

What is claimed is:

1. An embedded controller for a computer, comprising:
a processor;
first one or more logic elements comprising a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave;
second one or more logic elements comprising a platform environment control interface (PECI)-over-SPI engine, to:
build an SPI packet comprising an encapsulated PECI command; and
send a notification to an SPI master that the packet is available.

2. The embedded controller of claim 1 , wherein the SPI bus is an enhanced SPI (eSPI) bus.

3. The embedded controller of claim 2 , wherein the packet is an eSPI out-of-band (OOB) packet.

4. The embedded controller of claim 3 , wherein the OOB packet comprises an eSPI header and a PECI OOB payload.

5. The embedded controller of claim 1 , wherein the PECI-over-SPI engine is further to receive a PECI response via the SPI bus.

6. The embedded controller of claim 5 , wherein the PECI response comprises an SPI header and a PECI response payload.

7. A platform controller hub (PCH), comprising:
a processor;
an SPI network module to communicatively couple the PCH to a serial peripheral interface (SPI) bus as an SPI master; and
a platform environment control interface (PECI)-over-SPI master engine to:
receive via the SPI bus a notification that an encapsulated PECI packet is ready on an SPI slave;
fetch the encapsulated PECI packet from the SPI slave via the SPI bus; and
send the encapsulated PECI packet to a processor via the SPI bus.

8. The platform controller hub of claim 7 , wherein the PECI-over-Platform controller hub engine is further to:
receive a PECI response from the processor; and
send the response packet to the SPI slave via the SPI bus.

9. The platform controller hub of claim 8 , wherein the PECI-over-Platform controller hub engine is to reformat the response packet before forwarding it to an embedded controller (EC).

10. The platform controller hub of claim 9 , wherein reformatting the packet comprises reformatting it into a format comprising an SPI header and an out-of-band PECI response payload.

11. The platform controller hub of claim 7 , wherein the SPI bus is an enhanced SPI (eSPI) bus.

12. The platform controller hub of claim 11 , wherein the encapsulated PECI packet is an eSPI out-of-band (OOB) packet.

13. The platform controller hub of claim 12 , wherein the OOB packet comprises an SPI header and a PECI OOB payload.

14. At least one non-transitory machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
communicatively couple an embedded controller to a serial peripheral bus (SPI) bus as an SPI slave;
build an SPI packet comprising an encapsulated platform environment control interface (PECI) command; and
send a notification to an SPI master that the packet is available.

15. The at least one machine accessible storage medium of claim 14 , wherein the SPI bus is an enhanced SPI (eSPI) bus.

16. The at least one machine accessible storage medium of claim 15 , wherein the packet is an eSPI out-of-band (OOB) packet.

17. The at least one machine accessible storage medium of claim 16 , wherein the OOB packet comprises an eSPI header and a PECI OOB payload.

18. The at least one machine accessible storage medium of claim 14 , wherein the code further instructs the machine to receive a PECI response via the SPI bus.

19. The at least one machine accessible storage medium of claim 18 , wherein the PECI response comprises an SPI header and a PECI response payload.

20. At least one machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
communicatively couple a platform controller hub (PCH) to a serial peripheral interface (SPI) bus as an SPI master;
receive via the SPI bus a notification that an encapsulated platform environment control interface (PECI) packet is ready on an SPI slave;
fetch the encapsulated PECI packet from the SPI slave via the SPI bus; and
send the encapsulated PECI packet to a processor via the SPI bus.

21. The at least one machine accessible storage mediums of claim 20 , wherein the code further causes the machine to:
receive a PECI response from the processor; and
send the response packet to the SPI slave via the SPI bus.

22. The at least one machine accessible storage mediums of claim 21 , wherein the code further causes the machine to reformat the response packet before forwarding it to an embedded controller.

23. The at least one machine accessible storage mediums of claim 22 , wherein reformatting the packet comprises reformatting it into a format comprising an SPI header and an out-of-band PECI response payload.

24. The at least one machine accessible storage mediums of claim 20 , wherein the SPI bus is an enhanced SPI (eSPI) bus.

25. The at least one machine accessible storage mediums of claim 24 , wherein the encapsulated PECI packet is an eSPI out-of-band (OOB) packet.

26. The at least one machine accessible storage mediums of claim 25 , wherein the OOB packet comprises an SPI header and a PECI OOB payload.

Assignees

• Intel Corp

Inventors

• Hunsaker Mikal C
• Conrad Shaun M
• Zhu Zhenyu
• Singh Navtej

Classifications

• G06F13/362

  with centralised access control · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4068

  Electrical coupling · CPC title