Distributed input/output virtualization

US11086703B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11086703-B2
Application numberUS-201816055247-A
CountryUS
Kind codeB2
Filing dateAug 6, 2018
Priority dateFeb 11, 2016
Publication dateAug 10, 2021
Grant dateAug 10, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure includes apparatuses and methods related to distributed input/output (I/O) virtualization. A number of embodiments include an apparatus comprising a host computing device, a distributed virtualization controller (DVC) disposed on the host computing device, and a virtualized input/output (I/O) device in communication with the DVC.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: a management host computing device configured to coordinate virtualization functionality among a plurality of host computing devices communicatively coupled to the management host computing device; a virtualized input/output (I/O) device sharing resources between the management host computing device and the plurality of host computing devices, wherein the virtualized I/O device is a network interface card (NIC) or a graphics rendering device; and respective distributed virtualization controllers (DVCs) physically disposed on each of the management host computing device and the plurality of host computing devices, wherein: the respective DVCs comprise respective application specific integrated circuits (ASICs); and each respective DVC is to virtualize the I/O device to the host computing device on which the DVC is physically disposed. 2. The apparatus of claim 1 , wherein the management host computing device is in communication with a network switch. 3. The apparatus of claim 2 , wherein the management host computing device is configured to initiate a recovery mechanism on a physical I/O device in communication with the DVC in response to an error condition. 4. The apparatus of claim 1 , wherein the DVC is configured to expose at least one queue to the management host computing device and at least one of the plurality of host computing devices. 5. The apparatus of claim 4 , wherein the at least one queue is part of a multi-queue interface. 6. The apparatus of claim 4 , wherein the at least one queue is associated with a multi-function I/O device. 7. The apparatus of claim 1 , wherein each respective DVC comprises a virtualization layer and a physical layer, the virtualization layer exposes at least one peripheral device to the management host computing device and at least one of the plurality of host computing devices, and the physical layer provides an interface between a physical I/O device and the management host computing device and at least one of the plurality of host computing devices. 8. The apparatus of claim 7 , wherein the at least one peripheral device is a peripheral component interconnect express (PCIe) device. 9. The apparatus of claim 1 , wherein each respective DVC configures a virtual I/O device based at least in part on the management host computing device or at least one of the plurality of computing devices detecting a peripheral device. 10. The apparatus of claim 1 , wherein each respective DVC is configured to map a function associated with a physical I/O device to a virtualized I/O device on the respective DVC to provide communication between the virtualized I/O device and the respective DVC. 11. A system, comprising: a first host computing device including a first distributed virtualization controller (DVC) comprising circuitry physically disposed on the first host computing device; a second host computing device including a second DVC comprising circuitry physically disposed on the second host computing device, wherein the first DVC is configured to virtualize the at least one virtualized I/O device to the first host computing device, and wherein the second DVC is configured to virtualize the at least one virtualized I/O device to the second host computing device; a management host computing device including a third DVC comprising circuitry physically disposed on the management host computing device, wherein the management host computing device is configured to coordinate virtualization functionality among the first host computing device and the second host computing device, and wherein the first DVC, the second DVC, and the third DVC each comprise respective application specific integrated circuits (ASICs); a virtualized input/output (I/O) device sharing resources between the first host computing device and the second host computing device, wherein the virtualized I/O device is a network interface card (NIC) or a graphics rendering device; and a network switch in communication with the first host computing device and the second host computing device. 12. The system of claim 11 , wherein the management host computing device is in communication with the first host computing device and the second host computing device via a switch. 13. The system of claim 11 , further comprising a plurality of queue base address registers (QBARs) associated with the at least one virtualized I/O device. 14. The system of claim 13 , wherein a first QBAR associated with the at least one virtualized I/O device is mapped to the first host computing device, and a second QBAR associated with the at least one virtualized I/O device is mapped to the second host computing device. 15. The system of claim 11 , wherein an I/O transaction from the I/O device traverses the network switch only once. 16. A method, comprising: receiving an input/output (I/O) transaction via a virtualized input/output (I/O) device configured to share resources between a first computing device and a second computing device at a distributed virtualization controller (DVC) comprising an application-specific integrated circuit physically coupled to a host computing device, wherein the virtualized I/O device is a network interface card (NIC) or a graphics rendering device; coordinating, by a management host computing device comprising a management host DVC comprising circuitry disposed on the management host, wherein the management host is communicatively coupled to the first computing device and the second computing device, virtualization functionality of the first computing device and the second computing device; and virtualizing the I/O transaction to the host computing device on which the DVC is physically coupled. 17. The method of claim 16 , further comprising modifying an address associated with the I/O transaction. 18. The method of claim 17 , further comprising modifying an address associated with the I/O transaction concurrently with receiving the I/O transaction at the DVC. 19. The method of claim 16 , further comprising generating, by the DVC, an error indication in response to an error being detected by the DVC. 20. The method of claim 19 , further comprising initiating a recovery mechanism on the physical I/O in response to the error indication being generated.

Assignees

Inventors

Classifications

  • Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements · CPC title

  • Hypervisor-specific management and integration aspects · CPC title

  • I/O management, e.g. providing access to device drivers or storage · CPC title

  • Configuration setting · CPC title

  • using interrupt (G06F13/32 takes precedence) · CPC title

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Frequently asked questions

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What does patent US11086703B2 cover?
The present disclosure includes apparatuses and methods related to distributed input/output (I/O) virtualization. A number of embodiments include an apparatus comprising a host computing device, a distributed virtualization controller (DVC) disposed on the host computing device, and a virtualized input/output (I/O) device in communication with the DVC.
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H04L41/0895. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 10 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).