Circuitry and methods

Patent metadata

Field	Value
Publication number	US-11086626-B2
Application number	US-201916662396-A
Country	US
Kind code	B2
Filing date	Oct 24, 2019
Priority date	Oct 24, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

Circuitry comprises decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and execution circuitry to execute the program instructions; in which: the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction.

First claim

The invention claimed is:

1. Circuitry comprising:
decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and
execution circuitry to execute the program instructions;
wherein:
the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction;
the execution circuitry comprises two or more execution pipelines and a control circuitry to route a program instruction to a selected one of the two or more execution pipelines;
the control circuitry is configured to route a program instruction to an execution pipeline of the two or more execution pipelines in response to the hint data associated with that program instruction or another program instruction; and
when the hint data indicates that only one consumer instruction requires, as an input operand, the result generated by the given producer instruction, the control circuitry is configured to route that one consumer instruction and the given producer instruction to the same execution pipeline.

2. The circuitry of claim 1 , comprising communication circuitry to communicate a result of execution by one of the execution pipelines to one or more other of the execution pipelines for use as an execution input, in which:
when the hint data indicates that only one consumer instruction requires, as an input operand, the result generated by the given producer instruction, the communication circuitry is configured to communicate the result of execution of the given producer instruction only to that one of the execution pipelines to which the one consumer instruction is routed.

3. The circuitry of claim 1 , in which:
the execution circuitry comprises result storage to store the result of execution of a program instruction; and
the execution circuitry is configured to vary the storage of the result of execution of a given producer instruction in response to the hint data associated with the given producer instruction.

4. The circuitry of claim 3 , in which:
the result storage comprises a physical register file; and
the execution circuitry is configured to selectively inhibit writing of the result of execution of a given producer instruction to the physical register file in response to the hint data associated with the given producer instruction.

5. The circuitry of claim 4 , in which:
the execution circuitry is configured to selectively inhibit writing of the result of execution of a given producer instruction to the physical register file in response to initiation of execution of the number of consumer instructions defined by the hint data for the given producer instruction and which require, as an input operand, the result generated by the given producer instruction.

6. The circuitry of claim 3 , in which:
the result storage comprises a result cache; and
the execution circuitry is configured to control retention in the result cache of the result of execution of the given producer instruction in response to the hint data associated with the given producer instruction.

7. The circuitry of claim 6 , in which the execution circuitry is configured to control retention in the result cache of the result of execution of a given producer instruction at least until execution has been initiated for the number of consumer instructions defined by the hint data for the given producer instruction and which require, as an input operand, a result generated by the given producer instruction.

8. The circuitry of claim 1 , in which:
the execution circuitry comprises processing circuitry to execute a function equivalent to the operation of a predetermined group of program instructions; and
the decoder circuitry is configured to detect, in the set of program instructions, the predetermined group of program instructions and, in response to the hint data associated with at least one of the detected program instructions, to initiate execution by the execution circuitry of the function equivalent to the detected group of program instructions.

9. The circuitry of claim 8 , in which the decoder circuitry is configured to initiate execution of the function equivalent to the detected group of program instructions when the hint data associated with at least one of the detected group of program instructions indicates that at least one intermediate result of the detected group of program instructions has no consumer instructions other than instructions within the detected group of program instructions.

10. The circuitry of claim 1 , in which:
the hint data comprises n-bit hint data, where n is at least one, the n-bit hint data selectively representing at least one hint state for the given producer instruction in which a predetermined number of other instructions require, as an input operand, a result generated by the given producer instruction.

11. The circuitry of claim 10 , in which the predetermined number of other instructions comprises one other instruction.

12. The circuitry of claim 1 , in which:
each instruction is represented by an m-bit operation code defining at least an instruction operation, zero or more input operands and zero or more destination operands; and
the hint data is represented by one or more bits of the m-bit operation code.

13. A method comprising:
decoding program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction;
executing the program instructions by two or more execution pipelines; and
controlling operation of the executing step in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of other instructions which require, as an input operand, a result generated by the given producer instruction, wherein:
the executing step comprises routing a program instruction to a selected one of the two or more execution pipelines;
the routing is responsive to the hint data associated with that program instruction or another program instruction; and
when the hint data indicates that only one consumer instruction requires, as an input operand, the result generated by the given producer instruction, the routing comprises routing that one consumer instruction and the given producer instruction to the same execution pipeline.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Grubisic Roko
• Gabrielli Giacomo
• Horsnell Matthew James
• Zaidi Syed Ali Mustafa

Classifications

• G06F8/433

  Dependency analysis; Data or control flow analysis · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3824

  Operand accessing · CPC title