Efficient storage system battery backup usage through dynamic implementation of power conservation actions

Patent metadata

Field	Value
Publication number	US-11086379-B2
Application number	US-201916665053-A
Country	US
Kind code	B2
Filing date	Oct 28, 2019
Priority date	Oct 28, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

Power conservation logic for a storage node operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from volatile memory to non-volatile managed drives. The power conservation logic serially implements power conservation actions until enough reserve power is available to complete the emergency shutdown process. The power conservation logic may learn how much power savings are realized from each conservation action and adjust the order in which the conservation actions are serially implemented, e.g. in order from greatest to least power consumption reduction.

First claim

What is claimed is:

1. A method comprising:
implementing parallel processes with a storage node, comprising:
an emergency shutdown process comprising:
engaging an emergency power source; and
destaging data and metadata from volatile memory to non-volatile storage; and

a power conservation process comprising:
serially implementing ones of a plurality of power conservation actions until enough reserve power is available to complete the emergency shutdown process.

2. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises reducing processor power level.

3. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises depowering unused managed drives and associated interfaces.

4. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises parking unnecessary processor cores.

5. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises depowering host interfaces.

6. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises reducing processor clock speed.

7. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises reducing memory clock speed.

8. The method of claim 1 wherein serially implementing ones of the plurality of power conservation actions comprises reducing system cooling.

9. The method of claim 1 comprising estimating power savings from each of the conservation actions.

10. The method of claim 9 comprising implementing the power conservation actions serially in an order based on the estimated power savings.

11. An apparatus comprising:
a storage node comprising:
at least one computing node comprising volatile memory and a processor;
a plurality of non-volatile managed drives; and
power conservation logic that operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from the volatile memory to non-volatile managed drives, the power conservation logic comprising power conservation actions that are serially implemented until enough reserve power is available to complete the emergency shutdown process.

12. The apparatus of claim 11 wherein the power conservation actions comprise instructions that reduce processor power level.

13. The apparatus of claim 11 wherein the power conservation actions comprise instructions that depower unused managed drives and associated interfaces.

14. The apparatus of claim 11 wherein the power conservation actions comprise instructions that park unnecessary processor cores.

15. The apparatus of claim 11 wherein the power conservation actions comprise instructions that depower host interfaces.

16. The apparatus of claim 11 wherein the power conservation actions comprise instructions that reduce processor clock speed.

17. The apparatus of claim 11 wherein the power conservation actions comprise instructions that reduce memory clock speed.

18. The apparatus of claim 11 wherein serially implementing ones of the plurality of power conservation actions comprises reducing system cooling.

19. The apparatus of claim 11 wherein the power conservation logic estimates power savings from each of the conservation actions.

20. The apparatus of claim 19 wherein the power conservation logic implements the power conservation actions serially in an order based on the estimated power savings.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Guyer James
• Lim Clifford
• Gordon Scott

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3215

  Monitoring of peripheral devices · CPC title

• G06F1/30 Primary

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title