Apparatus and method for early lifetime failure detection system
US-2020408834-A1 · Dec 31, 2020 · US
Circuit aging detection sensor based on lookup table
US11085962B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11085962-B2 |
| Application number | US-201916676436-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 7, 2019 |
| Priority date | Nov 7, 2018 |
| Publication date | Aug 10, 2021 |
| Grant date | Aug 10, 2021 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.
First claim
Opening claim text (preview).
What is claimed is: 1. A circuit aging detection sensor based on a lookup table (LUT), comprising: a control circuit for generating a clock signal and two paths of control voltage, a first voltage controlled oscillator, a second voltage controlled oscillator, a first shaping circuit, a second shaping circuit, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array, and a digital-analogue converter, wherein the control circuit has a clock signal output terminal, a first voltage output terminal and a second voltage output terminal; the phase comparator has a clock terminal, a first input terminal, a second input terminal and an output terminal; the 3-digit voter has a clock terminal, an input terminal and an output terminal; the 8-digit counter has an input terminal, a setting terminal and an 8-digit parallel output terminal; the latch has a setting terminal, an 8-digit parallel input terminal and an 8-digit parallel output terminal; the lookup table array has an 8-digit parallel control terminal, a 16-digit parallel input terminal and an 8-digital parallel output terminal; the digital-analogue converter has an 8-digital parallel input terminal and an output terminal; the clock signal output terminal of the control circuit is respectively connected with the clock terminal of the phase comparator, the clock terminal of the 3-digit voter and the input terminal of the 8-digit counter; the first voltage output terminal of the control circuit is connected with the input terminal of the first voltage controlled oscillator; the second voltage output terminal of the control circuit is connected with the input terminal of the second voltage controlled oscillator; the output terminal of the first voltage controlled oscillator is connected with the input terminal of the first shaping circuit; the output terminal of the second voltage controlled oscillator is connected with the input terminal of the second shaping circuit; the output terminal of the first shaping circuit is connected with the first input terminal of the phase comparator; the output terminal of the second shaping circuit is connected with the second input terminal of the phase comparator; the output terminal of the phase comparator is connected with the input terminal of the 3-digit voter; the output terminal of the 3-digit voter is connected with the input terminal of the beat-frequency oscillator; the output terminal of the beat-frequency oscillator is respectively connected with the setting terminal of the 8-digit counter and the setting terminal of the latch; the 8-digit parallel output terminal of the 8-digit counter is connected with the 8-digit parallel input terminal of the latch; the 8-digit parallel output terminal of the latch is connected with the 8-digit parallel control terminal of the lookup table array; the 8-digit parallel output terminal of the lookup table array is connected with the 8-digit parallel input terminal of the digital-analogue converter. 2. The circuit aging detection sensor based on the LUT according to claim 1 , wherein the first voltage controlled oscillator includes 33 voltage controlled oscillator (VCO) units; each one of the VCO units has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a power terminal and a grounding terminal; the power terminals of all 33 VCO units are connected to a power supply, and the grounding terminals of all 33 VCO units are grounded; the first input terminal of the first VCO unit is connected with the first output terminal of the 33rd VCO unit, and the connecting terminal is the output terminal of the first voltage controlled oscillator; the second input terminal of the first VCO unit is connected with the second output terminal of the 33rd VCO unit; the first output terminal of the kth VCO unit is connected with the first input terminal of the (K+1)th VCO unit; the second output terminal of the kth VCO unit is connected with the second input terminal of the (K+1)th VCO unit, k+1, 2, . . . , 32; each one of the VCO units includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the connecting terminal is the power terminal of the VCO unit; the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are connected with the drain electrode of the second NMOS tube, and the connecting terminal is the first output terminal of the VCO unit; the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected with the drain electrode of the first NMOS tube, and the connecting terminal is the second output terminal of the VCO unit; the grid electrode of the first NMOS tube is the first input terminal of the VCO unit; the grid electrode of the second NMOS tube is the second input terminal of the VCO unit; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the connecting terminal is the grounding terminal of the VCO unit; the circuit structure of the second voltage controlled oscillator is identical with the circuit structure of the first voltage controlled oscillator. 3. The circuit aging detection sensor based on the LUT according to claim 1 , wherein the first shaping circuit includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube and a first phase inverter; the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are both connected to the power supply; the grid electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube are connected with the drain electrode of the fourth NMOS tube, and the connecting terminal is the output terminal of the first shaping circuit; the drain electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the input terminal of the first phase inverter, and the connecting terminal is the input terminal of the first shaping circuit; the output terminal of the first phase inverter is connected with the grid electrode of the fourth NMOS tube; the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are both grounded; the circuit structure of the second shaping circuit is identical with the circuit structure of the first shaping circuit. 4. The circuit aging detection sensor based on the LUT according to claim 1 , wherein the phase comparator includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a second phase inverter, a third phase inverter, a fourth phase inverter and a first two-input AND gate; the first two-input AND gate has a first input terminal, a second input terminal and an output terminal; the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected to the power supply; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube, and the connecting terminal is the clock terminal of the phase comparator; the drain electrode of the fifth PMOS tube, the drain electrode of the sixth NMOS tube and the grid electrode of the sixth PMOS tube are connected with the input terminal of the second phase inverter; the drain electrode of the sixth PMOS tube, the output terminal of the second phase inverter and the drain electrode of the fifth NMOS tube are connected with the input terminal of the third phase inverter; the grid electrode of the s
Assignees
Inventors
Classifications
the characteristic being duration, interval, position, frequency, or sequence · CPC title
comprising logic circuits · CPC title
the amplifier comprising one or more field effect transistors · CPC title
- H03K3/0322Primary
with differential cells · CPC title
using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title
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Frequently asked questions
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- What does patent US11085962B2 cover?
- The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-…
- Who is the assignee on this patent?
- Univ Ningbo
- What technology area does this patent fall under?
- Primary CPC classification H03K3/0322. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 10 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).