Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop

Patent metadata

Field	Value
Publication number	US-11082271-B2
Application number	US-202016900010-A
Country	US
Kind code	B2
Filing date	Jun 12, 2020
Priority date	Jul 1, 2016
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

First claim

What is claimed is:

1. An apparatus comprising:
a first bandwidth phase lock loop with a first input adapted to be coupled to a data signal generator, a second input, a first output, and a second output;
a fast phase change detection circuit having a first input, a second input, and an output, the first input is coupled to the first output of the first bandwidth phase lock loop, and the second input is coupled to the second output of the first bandwidth phase lock loop, the fast phase change detection circuit is configured to:
generate a fast phase change detection signal by comparing a first signal at the first input and a second signal at the second input;
output, at the first output of the fast phase change detection circuit, the fast phase change detection signal.

2. The apparatus of claim 1 , wherein the first bandwidth phase lock loop includes:
a first phase frequency detector to (A) receive the data signal and the first output signal and (B) output a first pulse signal corresponding to a first phase difference between the data signal and the first output signal;
a second phase frequency detector to (A) receive the data signal and the second output signal and (B) output a second pulse signal corresponding to a second phase difference between the data signal and the second output signal, the first output signal oscillating at the first phase and the second output signal oscillating at the second phase;
a voltage controlled oscillator to output the first output signal and the second output signal; and
a first multiplexer to use the output of the fast phase change detection circuit as a first select signal and output the first pulse signal or the second pulse signal based on the first select signal, the output of the first multiplexer being used in the feedback loop of the first bandwidth phase lock loop.

3. The apparatus of claim 2 , wherein the first multiplexer is structured to receive the first pulse signal and the second pulse signal.

4. The apparatus of claim 2 , wherein the first multiplexer is structured to:
output the first pulse signal when the output of the fast phase change detection circuit is the first logic value; and
output the second pulse signal when the output of the fast phase change detection circuit is the second logic value.

5. The apparatus of claim 2 , wherein the voltage controlled oscillator is structured to output the first output signal or the second output signal based on the output of the first multiplexer.

6. A method comprising:
receiving, by a first bandwidth phase lock loop, a data signal at a first phase;
outputting, by a first output of the first bandwidth phase lock loop, a first output signal at the first phase;
outputting, by a second output of the first bandwidth phase lock loop, a second output signal at the second phase;
generating, by a fast phase change detection circuit, a fast phase change detection signal based on a comparison of the first output signal and the second output signal; and
transmitting, from the fast phase change detection circuit to the first bandwidth phase lock loop, the fast phase change detection signal.

7. The method of claim 6 , wherein the first bandwidth phase lock loop includes:
receiving, by a first phase frequency detector, the data signal and the first output signal;
outputting, by the first phase frequency detector, a first pulse signal corresponding to a first phase difference between the data signal and the first output signal;
receiving, by a second phase frequency detector, the data signal and the second output signal;
outputting, by the second phase frequency detector, a second pulse signal corresponding to a second phase difference between the data signal and the second output signal, the first output signal oscillating at the first phase and the second output signal oscillating at the second phase;
outputting, by a voltage controlled oscillator, the first output signal and the second output signal;
using, by a first multiplexer, the output of the fast phase change detection circuit as a first select signal;
outputting, by the first multiplexer, the first pulse signal or the second pulse signal based on the first select signal, the output of the first multiplexer being used in the feedback loop of the first bandwidth phase lock loop.

8. The apparatus of claim 7 , further comprising receiving, by the first multiplexer, the first pulse signal and the second pulse signal.

9. The apparatus of claim 7 , further comprising:
outputting, by the first multiplexer, the first pulse signal when the output of the fast phase change detection circuit is the first logic value; and
outputting, by the first multiplexer, the second pulse signal when the output of the fast phase change detection circuit is the second logic value.

10. The method of claim 7 , further comprising outputting, by the voltage controller oscillator, the first output signal or the second output signal based on the output of the first multiplexer.

Assignees

• Texas Instruments Inc

Inventors

• Mukherjee Subhashish
• Patki Abhijit Anant
• Bonu Madhulatha
• Shrivastava Kumar Anurag

Classifications

• H04L27/2272 Primary

  using phase locked loops (H04L27/2273 takes precedence) · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03L7/113

  using frequency discriminator · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title