Adaptive equalization using correlation of data patterns with errors

Patent metadata

Field	Value
Publication number	US-11082268-B2
Application number	US-202017065043-A
Country	US
Kind code	B2
Filing date	Oct 7, 2020
Priority date	Apr 27, 2006
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

First claim

What is claimed is:

1. An integrated circuit comprising:
an input port to receive a distorted signal having a first frequency component and a second frequency component;
an equalizer to equalize the distorted signal, the equalizer and treat the first frequency component to a first amplification factor and the second frequency component to a second amplification factor different from the first amplification factor to produce an equalized signal from the distorted signal;
a sampler to sample the equalized signal to produce a series of samples, the series of samples expressing patterns; and
equalizer control circuitry to detect a phase of the equalized signal from the series of samples and adjust the first amplification factor relative to the second amplification factor responsive to a subset of the patterns.

2. The integrated circuit of claim 1 , the equalizer control circuitry comprising:
a phase detector to detect a phase of the distorted signal; and
logic to adjust the first amplification factor relative to the second amplification factor responsive to the subset of the patterns and the phase of the distorted signal.

3. The integrated circuit of claim 2 , further comprising and edge sampler to produce a series of edge samples, the logic to sense the phase of the distorted signal using the series of edge samples.

4. The integrated circuit of claim 2 , the equalizer control circuitry comprising a bit correlator to issue a match signal to the logic responsive to the subset of the patterns.

5. The integrated circuit of claim 2 , further comprising a clock-recovery circuit to provide a clock signal to the sampler and adjust the clock signal responsive to the phase of the distorted signal.

6. The integrated circuit of claim 1 , wherein the sampler is a first sampler and the series of samples a first series of samples, the integrated circuit further comprising a second sampler to sample the equalized signal to produce a second series of samples alternating with the first series of samples.

7. The integrated circuit of claim 1 , further comprising an edge sampler to sample the equalized signal to produce a series of edge samples expressing edge timing, the equalizer control circuitry coupled to adjust the first amplification factor relative to the second amplification factor responsive to the edge timing.

8. A method of equalizing a distorted signal expressing a series of symbols, the distorted signal having a first frequency component and a second frequency component, the method comprising:
equalizing the distorted signal to create an equalized signal, the equalizing including adjusting an amplitude of first frequency component relative to the second frequency component to create the equalized signal;
sampling the equalized signal on edges of a data clock signal to acquire a series of data samples;
sampling the equalized signal on edges of an edge clock signal to acquire a series of edge samples;
phase aligning the data clock signal to the equalized signal responsive to the data samples and the edge samples; and
adjusting the amplitude of the first frequency component of the distorted signal relative to the second frequency component of the distorted signal responsive to the data samples and the edge samples.

9. The method of claim 8 , further comprising detecting a pattern in the series of data samples and adjusting the amplitude of the first frequency component of the distorted signal relative to the second frequency component of the distorted signal responsive to the detected pattern.

10. The method of claim 9 , further comprising, for a subset of the edge samples associated with the pattern, detecting pattern-specific early bits and adjusting the amplitude of the first frequency component relative to the second frequency component responsive to the pattern-specific early bits.

11. The method of claim 10 , further comprising, for a subset of the edge samples associated with the pattern, detecting pattern-specific late bits and adjusting the amplitude of the first frequency component relative to the second frequency component responsive to the pattern-specific late bits.

12. The method of claim 9 , further comprising, for a subset of the edge samples associated with the pattern, detecting pattern-specific late bits and adjusting the amplitude of the first frequency component relative to the second frequency component responsive to the pattern-specific late bits.

13. The method of claim 12 , further comprising, for a subset of the edge samples associated with the pattern, detecting pattern-specific early bits and adjusting the amplitude of the first frequency component relative to the second frequency component responsive to the pattern-specific early bits.

14. The method of claim 13 , wherein the adjusting of the amplitude of the first frequency component relative to the second frequency component is responsive to a ratio of the early bits to the late bits.

15. The method of claim 8 , further comprising:
detecting a first pattern in the series of data samples, the first pattern associated with the first frequency component;
detecting first phase errors associated with the first pattern in the series of data samples;
detecting a second pattern in the series of data samples, the second pattern associated with the second frequency component;
detecting second phase errors associated with the second pattern in the series of data samples; and
adjusting the amplitude of the first frequency component of the distorted signal relative to the second frequency component of the distorted signal responsive to the first phase errors and the second phase errors.

16. An integrated-circuit receiver comprising:
a receive port to receive a distorted signal having a first frequency component and a second frequency component;
an equalizer coupled to the receive port to equalize the distorted signal to create an equalized signal, the equalizer adjusting an amplitude of the first frequency component relative to the second frequency component to create the equalized signal;
a data sampler to sample the equalized signal on edges of a data clock signal to acquire a series of data samples;
an edge sampler to sample the equalized signal on edges of an edge clock signal to acquire a series of edge samples;
equalizer control circuitry to detect phase of the edge clock signal responsive to the data samples and the edge samples and control the equalizer to adjust the amplitude of the first frequency component relative to the second frequency component responsive to the phase of the edge clock signal; and
a clock-recovery circuit to phase align the data clock signal with the equalized signal responsive to the phase of the edge clock signal.

17. The receiver of claim 16 , the equalizer control circuitry further comprising a bit correlator to detect a pattern in the series of data samples, the equalizer control circuit to adjust the amplitude of the first frequency component relative to the second frequency component responsive to the detected pattern.

18. The receiver of claim 17 , the equalizer control circuitry, for a subset of the edge samples associated with the pattern, detecting pattern-specific error bits and adjusting the amplitude of the first frequency component relative to the second frequency component responsive to the pattern-specific error bits.

19. The receiver of claim 18 , wherein the pattern-specific error bits include at least one of early bits and late bits.

20. The receiver of claim 19 , wherein the adjusting of t

Assignees

• Rambus Inc

Inventors

• Palmer Robert E

Classifications

• H04L7/041 Primary

  using special codes as synchronising signal · CPC title

• H04L25/03273

  with carrier recovery circuitry · CPC title

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L25/069

  by detecting edges or zero crossings · CPC title

• H04L25/03006

  Arrangements for removing intersymbol interference · CPC title