Clock distribution circuit using adjustable phase control and voltage converter including the same

Patent metadata

Field	Value
Publication number	US-11082050-B2
Application number	US-202017000642-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Dec 13, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A clock distribution circuit including a Phase Locked Loop (PLL), a first Phase Detecting and Converting (PDC) circuit, a second PDC circuit, and a clock generating and compensating (CGC) circuit may be provided. The PLL may generate reference clock signals. The first PDC circuit may generate input phase difference voltages based on phase differences between respective pairs of two reference clock signals among the reference clock signals. The second PDC circuit may generate output phase difference voltages based on phase differences between respective pairs of two power switching signals among power switching signals received from external switching regulators. The CGC circuit may generate input clock signals provided to the plurality of external switching regulators by shifting phases of the reference clock signals, and additionally control a phase of at least one of the input clock signals based on the input phase difference voltages and the output phase difference voltages.

First claim

What is claimed is:

1. A clock distribution circuit comprising:
a phase locked loop (PLL) configured to generate a plurality of reference clock signals;
a first phase detecting and converting circuit configured to generate a plurality of input phase difference voltages based on phase differences between respective pairs of two reference clock signals among the plurality of reference clock signals;
a second phase detecting and converting circuit configured to generate a plurality of output phase difference voltages based on phase differences between respective pairs of two power switching signals among a plurality of power switching signals received from a plurality of external switching regulators; and
a clock generating and compensating circuit configured to,
generate a plurality of input clock signals to be provided to the plurality of external switching regulators by shifting phases of the plurality of reference clock signals, and
control a phase of at least one of the plurality of input clock signals based on the plurality of input phase difference voltages and the plurality of output phase difference voltages.

2. The clock distribution circuit of claim 1 , wherein
the plurality of reference clock signals include a first reference clock signal and a second reference clock signal,
the plurality of external switching regulators include a first external switching regulator and a second external switching regulator,
the plurality of input clock signals include a first input clock signal and a second input clock signal,
the plurality of power switching signals include a first power switching signal and a second power switching signal, and
the clock generating and compensating circuit is configured to adjust a phase of one of the first and second input clock signals based on one of the plurality of input phase difference voltages and one of the plurality of output phase difference voltages such that a phase difference between the first and second power switching signals received from the first and second external switching regulators is equal to a phase difference between the first and second reference clock signals, based on which the first and second input clock signals to be provided to the first and second external switching regulators are generated.

3. The clock distribution circuit of claim 1 , wherein the clock generating and compensating circuit includes:
a first voltage-to-delay converter (VDC) configured to generate a first reference voltage based on an input reference voltage, and generate a first input clock signal by shifting a phase of a first reference clock signal based on the first reference voltage; and
a second voltage-to-delay converter configured to,
generate a second reference voltage based on the first reference voltage,
generate a second input clock signal by shifting a phase of a second reference clock signal based on the second reference voltage, and
control a phase of the second input clock signal by adjusting a level of the second reference voltage based on a first input phase difference voltage and a first output phase difference voltage.

4. The clock distribution circuit of claim 3 , wherein the first voltage-to-delay converter includes:
a first amplifier including a first input terminal configured to receive the input reference voltage, a second input terminal connected to a first resistor, and an output terminal at which the first reference voltage is outputted;
a first transistor including a first electrode configured to receive a power supply voltage, a control electrode configured to receive the first reference voltage, and a second electrode at which a first feedback voltage is outputted; and
a first delay line configured to generate the first input clock signal by delaying the phase of the first reference clock signal based on the first feedback voltage.

5. The clock distribution circuit of claim 4 , wherein the second voltage-to-delay converter includes:
a second resistor including a first electrode configured to receive the first reference voltage, and a second electrode connected to a first node at which the second reference voltage is outputted;
a second amplifier including a first input terminal configured to receive the first input phase difference voltage, a second input terminal configured to receive the first output phase difference voltage, and an output terminal connected to the first node;
a second transistor including a first electrode configured to receive the power supply voltage, a control electrode configured to receive the second reference voltage, and a second electrode at which a second feedback voltage is outputted; and
a second delay line configured to generate the second input clock signal by delaying the phase of the second reference clock signal based on the second feedback voltage.

6. The clock distribution circuit of claim 3 , wherein the first phase detecting and converting circuit includes:
a first input phase-to-voltage converter (PVC) configured to generate the first input phase difference voltage based on a phase difference between the first reference clock signal and the second reference clock signal.

7. The clock distribution circuit of claim 6 , wherein the first input phase-to-voltage converter includes:
a first edge detector configured to generate a first phase difference pulse signal based on edges of the first reference clock signal and the second reference clock signal; and
a first low pass filter (LPF) configured to convert the first phase difference pulse signal into the first input phase difference voltage.

8. The clock distribution circuit of claim 7 , wherein the first edge detector includes:
a first flip-flop configured to generate the first phase difference pulse signal based on the first reference clock signal, the second reference clock signal and a power supply voltage.

9. The clock distribution circuit of claim 7 , wherein the first low pass filter includes:
a first resistor including a first electrode receiving the first phase difference pulse signal, and a second electrode connected to a first node at which the first input phase difference voltage is outputted; and
a first capacitor connected between the first node and a ground voltage.

10. The clock distribution circuit of claim 3 , wherein the second phase detecting and converting circuit includes:
a first output phase-to-voltage converter configured to generate the first output phase difference voltage based on a phase difference between a first power switching signal and a second power switching signal among the plurality of power switching signals.

11. The clock distribution circuit of claim 3 , wherein the clock generating and compensating circuit further includes:
a third voltage-to-delay converter configured to generate a third reference voltage based on the second reference voltage, generate a third input clock signal by shifting a phase of a third reference clock signal based on the third reference voltage, and control a phase of the third input clock signal by adjusting a level of the third reference voltage based on a second input phase difference voltage and a second output phase difference voltage.

12. The clock distribution circuit of claim 11 , wherein the first phase detecting and converting circuit includes:
a first input phase-to-voltage converter configured to generate the first input phase difference voltage by detecting a phase difference between the first reference clock signal and the second reference clock signal; and
a second input phase-to-voltage converter configured to generate the second input phase difference voltage by detecting a phase difference between the seco

Assignees

• Samsung Electronics Co Ltd

Inventors

• Nam Hyunseok

Classifications

• H02M1/0064

  Magnetic structures combining different functions, e.g. storage, filtering or transformation · CPC title

• H03H1/02

  RC networks, e.g. filters · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title