Memory interface system for duty-cycle error detection and correction

Patent metadata

Field	Value
Publication number	US-11082036-B2
Application number	US-201916453166-A
Country	US
Kind code	B2
Filing date	Jun 26, 2019
Priority date	Jun 26, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A method for duty cycle error detection and correction includes receiving, during a read operation performed on a memory cell, a first data strobe signal. The method also includes generating a second data strobe signal by phase delaying the first data strobe signal. The method also includes determining, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted. The method also includes adjusting a clock signal based on a determination that the duty cycle is distorted.

First claim

What is claimed is:

1. A method for duty cycle distortion detection and correction, the method comprising:
receiving, during a read operation performed on a memory cell, a first data strobe signal;
generating a second data strobe signal by phase delaying the first data strobe signal;
determining, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted; and
adjusting a clock signal based on a determination that the duty cycle is distorted.

2. The method of claim 1 , wherein the first data strobe signal is part of a differential pair.

3. The method of claim 1 , wherein generating the second data strobe signal by phase delaying the first data strobe signal includes phase delaying the first data strobe signal by 90 degrees.

4. The method of claim 1 , wherein the duty cycle includes a 50% duty cycle.

5. The method of claim 1 , further comprising, in response to a determination that the duty cycle is distorted, determining, based on the first data strobe signal and the second data strobe signal, whether the duty cycle is above a duty cycle threshold.

6. The method of claim 5 , wherein adjusting the clock signal based on the determination that the duty cycle is distorted includes, decreasing the clock signal in response to a determination that the duty cycle is above the duty cycle threshold.

7. The method of claim 5 , wherein adjusting the clock signal based on the determination that the duty cycle is distorted includes, increasing the clock signal in response to a determination that the duty cycle is not above the duty cycle threshold.

8. A controller comprising:
a bus interface in communication with one or more memory blocks of a memory system; and
a processor configured to:
receive, during a read operation performed on at least one memory cell of the one or more memory blocks, a first data strobe signal;
generate a second data strobe signal by phase delaying the first data strobe signal;
determine, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted; and
adjust a clock signal based on a determination that the duty cycle is distorted.

9. The controller of claim 8 , wherein the first data strobe signal is part of a differential pair.

10. The controller of claim 8 , wherein the processor is further configured to generate the second data strobe signal by phase delaying the first data strobe signal by 90 degrees.

11. The controller of claim 8 , wherein the duty cycle includes a 50% duty cycle.

12. The controller of claim 8 , wherein the processor is further configured to, in response to a determination that the duty cycle is distorted, determine, based on the first data strobe signal and the second data strobe signal, whether the duty cycle is above a duty cycle threshold.

13. The controller of claim 12 , wherein the processor is further configured to adjust the clock signal based on the determination that the duty cycle is distorted by decreasing the clock signal in response to a determination that the duty cycle is above the duty cycle threshold.

14. The controller of claim 12 , wherein the processor is further configured to adjust the clock signal based on the determination that the duty cycle is distorted by increasing the clock signal in response to a determination that the duty cycle is not above the duty cycle threshold.

15. A system for detecting and correcting duty cycle distortion, the system comprising:
at least one memory device; and
a controller in communication with the at least one memory device, the controller including:
a duty cycle detector configured to:
receive, during a read operation performed on the at least one memory device, a first data strobe signal from the at least one memory device;
generate a second data strobe signal by phase delaying the first data strobe signal; and
determine, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted;

a duty cycle correction circuit configured to:
receive a signal from the duty cycle detector indicating whether the duty cycle is distorted;
determine, in response to the signal from the duty cycle detector indicating that the duty cycle is distorted, whether the duty cycle is above a duty cycle threshold; and
decrease a clock signal based on a determination that the duty cycle is above the duty cycle threshold; and

a duty cycle connection circuit configured to communicate the clock signal to the at least one memory device.

16. The system of claim 15 , wherein the first data strobe signal is part of a differential pair.

17. The system of claim 15 , wherein the duty cycle includes a 50% duty cycle.

18. The system of claim 15 , wherein the duty cycle correction circuit is further configured to increase the clock signal based on the determination that the duty cycle is not above the duty cycle threshold.

19. The system of claim 15 , wherein the duty cycle correction circuit is further configured to determine whether the signal from the duty cycle detector and a previous signal from the duty cycle detector are the same.

20. The system of claim 19 , wherein the duty cycle correction circuit is further configured to:
determine, in response to the signal from the duty cycle detector indicating that the duty cycle is distorted, whether the duty cycle is above a duty cycle threshold, based on a determination that the signal from the duty cycle detector and the previous signal from the duty cycle detector are the same.

Assignees

• Sandisk Technologies Llc
• SanDiskTechnologies LLC

Inventors

• Marko Gilad
• Katz Arkady

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title