Systems and methods for TIA base current detection and compensation

Patent metadata

Field	Value
Publication number	US-11082010-B2
Application number	US-201816181523-A
Country	US
Kind code	B2
Filing date	Nov 6, 2018
Priority date	Nov 6, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Described herein are systems and methods that can adjust the performance of a transimpedance amplifier (TIA) in order to compensate for changing environmental and/or manufacturing conditions. In some embodiments, the changing environmental and/or manufacturing conditions may cause a reduction in beta of a bipolar junction transistor (BJT) in the TIA. A low beta may result in a high base current for the BJT causing the output voltage of the TIA to be formatted as an unusable signal output. To compensate for the low beta, the TIA generates an intermediate signal voltage, based on the base current and beta that is compared with the PN junction bias voltage on another BJT. Based on the comparison, the state of a digital state machine may be incremented, and a threshold base current is determined. This threshold base current may decide whether to compensate the operation of the TIA, or discard the chip.

First claim

What is claimed is:

1. A system comprising:
a current digital to analog converter (DAC) operable to generate an idac current based on a first state level of a digital state machine;
a transimpedance amplifier (TIA) operable to receive the idac current and to generate an intermediate signal voltage (VF) and generate an output voltage (Vout);
a comparator operable to receive the intermediate signal voltage (VF) and a reference voltage and generate an output; and
the digital state machine operable to generate a second state level based on the output of the comparator,
wherein, the current DAC changes its generated idac current if there is a difference between the first state level and the second state level.

2. The system of claim 1 , wherein if the intermediate signal voltage (VF) is greater than the reference voltage, the output of the comparator is a “1”, causing the digital state machine to increment a digital state from the first state level to the second state level, in turn causing the current DAC to increase the idac current.

3. The system of claim 2 , wherein if the digital state machine increments the digital state, the idac current increases, and the TIA repeats generation of another value of the intermediate signal voltage (VF) utilizing the increased idac current.

4. The system of claim 1 , wherein if the intermediate signal voltage (VF) is less than the reference voltage, the output of the comparator is a “0”, causing no change in a state level of the digital state machine, and causing no change to idac current coupled to the TIA.

5. The system of claim 4 , wherein, if the digital state machine does not increment to a higher level state, a current state is recorded and compared with a pre-determined state, and wherein, based on the comparison, a decision is made to 1) discard the TIA, or 2) continue operation with last adjusted idac current.

6. The system of claim 1 , wherein the TIA comprises a first bipolar junction transistor (first BJT), and the intermediate signal voltage (VF) is based in part on a value of beta of the first BJT.

7. The system of claim 6 , wherein a first base current (ib1) for the first BJT is equal to the current from the idac current plus a feedback current (ibf) received via a feedback resistor, wherein the intermediate signal voltage (VF) equals a voltage VBE1, which is primarily based on a barrier voltage, plus the feedback current (ibf) times a resistance of the feedback resistor.

8. The system of claim 7 , wherein a decrease in the value of beta of the first BJT, that causes an increase in the first base current (ib1), is neutralized by incrementing a digital state of the digital state machine in order to increase the idac current.

9. The system of claim 7 , wherein when the idac current equals the first base current (ib1), then the idac current increases in value to cause feedback current (ibf) to become negative, the comparator to transitions from a “1” to a “0”.

10. The system of claim 6 , wherein a variation of a beta of the first BJT causes an inverse variation of the intermediate signal voltage (VF) that in turn causes a change in a first base current (ib1) for the first BJT, wherein the change in the first base current (ib1) compensates for the variation in the beta.

11. The system of claim 6 , wherein the value of beta may vary depending on changes in environment, e.g. 1) temperature, and 2) silicon wafer manufacturing variations.

12. The system of claim 1 , wherein the reference voltage is based on a barrier voltage of a second BJT in the TIA.

13. The system of claim 1 , wherein an operation status of the TIA is based on a relationship between the intermediate signal voltage (VF) and an impedance of a load of the TIA.

14. The system of claim 13 , wherein when VF increases to a pre-determine value, the impedance of the load of the TIA decreases, causing the TIA to no longer operate.

15. A method comprising:
generating a DAC current by a current DAC and coupling the DAC current to a transimpedance amplifier (TIA);
generating, by the TIA, an intermediate signal voltage (VF) based on the DAC current, a base current and a value of beta of a bipolar junction transistor of the TIA;
comparing, by a comparator, the intermediate signal voltage (VF) and a reference voltage;
if the intermediate signal voltage (VF) is greater than the reference voltage and an output of the comparator changes, instructing a digital state machine to increment to a next digital code, causing the current DAC to increase its DAC current; and
repeating the generation of the intermediate signal voltage (VF) based on the increased DAC current.

16. The method of claim 15 , further comprising:
if the intermediate signal voltage (VF) is not greater than the reference voltage, recording a last digital code and comparing the last digital code with a pre-determined digital code.

17. The method of claim 16 , further comprising:
based on the comparison, deciding to 1) discard the TIA, or 2) continue operation with adjusted DAC current.

18. The method of claim 15 , wherein the bipolar junction transistor is a first bipolar junction transistor, and wherein the reference voltage is a bias voltage across a PN junction of a second bipolar junction transistor of the TIA.

19. A system comprising:
a current digital to analog converter (DAC) operable to generate an idac current based on a first state level of a digital state machine;
a transimpedance amplifier (TIA) comprising a first bipolar junction transistor (BJT) having an associated load, and a second BJT, operable to receive the idac current and to generate an intermediate signal voltage (VF) and generate an output voltage (Vout);
a comparator operable to receive the intermediate signal voltage (VF) and a reference voltage and generate an output; and
the digital state machine operable to generate a second state level based on the output of the comparator,
wherein, the current DAC changes its generated idac current if there is a difference between the first state level and the second state level.

20. The system of claim 19 , wherein when VF increases to a pre-determine value, an impedance of the associated load of the TIA decreases, causing the TIA to no longer operate.

21. The system of claim 19 , wherein if the intermediate signal voltage (VF) is greater than the reference voltage, the output of the comparator is at a “STATE1”, causing the digital state machine to increment a digital state from the first state level to the second state level, in turn causing the current DAC to increase the idac current, wherein if the intermediate signal voltage (VF) becomes less than the reference voltage, the output of the comparator is a “STATE2”, causing no change in a state level of the digital state machine, and causing no change to idac current coupled to the TIA.

Assignees

• Velodyne Lidar Inc
• Velodyne Lidar Usa Inc

Inventors

• Pinto Roger
• Venkatesan Pravin Kumar

Classifications

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03M1/742

  using current sources as quantisation value generators · CPC title

• H03G2201/40

  Combined gain and bias control · CPC title

• H03G3/3089

  Control of digital or coded signals · CPC title

• H03G3/007

  Control dependent on the supply voltage · CPC title