Circuits and methods for wearable device charging and wired control

US11081836B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11081836-B2
Application numberUS-202016875485-A
CountryUS
Kind codeB2
Filing dateMay 15, 2020
Priority dateOct 12, 2016
Publication dateAug 3, 2021
Grant dateAug 3, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and devices for wired charging and communication with a wearable device are described. In one embodiment, a symmetrical contact interface comprises a first contact pad and a second contact pad, and particular wired circuitry is coupled to the first and second contact pad to enable charging as well as receive and transmit communications via the contact pads as part of various device states.

First claim

Opening claim text (preview).

What is claimed is: 1. A wearable device configured for wired charging a charging and control comprising: a symmetrical contact interface comprising a first contact pad and a second contact pad; a first transistor having a first source connected to a device voltage terminal, a first gate connected to a first input path or a second input path, and a drain connected to the first input path or the second input path, wherein the first contact pad is connected to the first input path; a second transistor having a second source connected to the device voltage terminal, a second gate connected to the first input path or the second input path, and a second drain connected to the first input path or the second input path, wherein the second contact pad is connected to the second input path; a third transistor having a third source connected to a device ground, a third gate connected to the first input path or the second input path, and a third drain connected to the first input path or the second input path; and fourth transistor having a further source connected to the device ground, a fourth gate connected to the first input path or the second input path, and a fourth drain connected to the first input path or the second input path. 2. The wearable device of claim 1 , wherein the first transistor and the second transistor are p-type field effect (PFET) transistors. 3. The wearable device of claim 1 , wherein the third transistor and the fourth transistor are n type field effect (NFET) transistors. 4. The wearable device of claim 1 further comprising: a fifth transistor having a source connected to a first communication path coupled to control circuitry of the wearable device, a gate connected to a control input configured for selecting between a charging mode and a communication mode of the wearable device, and a drain connected to the first input path. 5. The wearable device of claim 1 wherein first transistor, second transistor, third transistor, and fourth transistor of the wearable device comprise a low resistance field effect transistor (HET). 6. The wearable device of claim 1 further comprising a first electrostatic discharge (ESD) protection element coupled from the first path to the device ground; and a second ESD protection element coupled from the second path to the device ground. 7. The wearable device of claim 6 wherein the first ESD protection element comprises an ESD diode. 8. The wearable device of claim 1 wherein the symmetrical contact interface further comprises a first coupling magnet and a second coupling magnet disposed on opposing sides of a line between the first contact pad and the second contact pad to create the symmetrical contact interface. 9. The wearable device of claim 8 wherein the wearable device comprises glasses; and wherein the symmetrical contact interface is further disposed in a temple portion of the glasses proximate to a first hinge, such that a first arm coupled to the temple portion via the first hinge covers the symmetrical contact interface of the first surface when the first arm is in an open position, and the first arm exposes the symmetrical contact interface of the first surface when the first arm is in a closed position. 10. The wearable device of claim 1 , wherein the first gate is connected to the second input path and the first drain is connected to the first input path. 11. The wearable device of claim 1 , wherein the second gate is connected to the first input path and the second drain is connected to the second input path. 12. The wearable device of claim 1 , wherein the third gate is connected to the second input path and the third drain is connected to the first input path. 13. The wearable device of claim 1 , wherein the fourth gate is connected to the first input path and the fourth drain is connected to the second input path. 14. An apparatus for charging a wearable device comprising: a first transistor having a first source connected to a device voltage terminal, a first gate connected to a first input path or a second input path, and a drain connected to the first input path or the second input path, wherein the first contact pad is connected to the first input path; a second transistor having a second source connected to the device voltage terminal, a second gate connected to the first input path or the second input path, and a second drain connected to the first input path or the second input path, wherein the second contact pad is connected to the second input path; a third transistor having a third source connected to a device ground, a third gate connected to the first input path or the second input path, and a third drain connected to the first input path or the second input path; and fourth transistor having a further source connected to the device ground, a fourth gate connected to the first input path or the second input path, and a fourth drain connected to the first input path or the second input path. 15. The apparatus of claim 14 , wherein the first transistor and the second transistor are p-type field effect (PFET) transistors and the third transistor and the fourth transistor are n type field effect (NFET) transistors. 16. The apparatus of claim 14 , wherein the first gate is connected to the second input path and the first drain is connected to the first input path. 17. The apparatus of claim 14 , wherein the second gate is connected to the first input path and the second drain is connected to the second input path. 18. The apparatus of claim 14 , wherein the third gate is connected to the second input path and the third drain is connected to the first input path. 19. The apparatus of claim 14 , wherein the fourth gate is connected to the first input path and the fourth drain is connected to the second input path. 20. An apparatus for wired charging and control comprising: a chargeable device comprising a symmetrical contact interface comprising a first contact pad and a second contact pad; means for accepting a charge input via the first contact pad and the second contact pad; means for receiving control data via the first contact pad and the second contact pad; and means for transmitting device data via the first contact pad and the second contact pad.

Assignees

Inventors

Classifications

  • against overdischarge · CPC title

  • against overcharge · CPC title

  • with electronic devices having internal batteries, e.g. mobile phones · CPC title

  • Battery or charger load switching, e.g. concurrent charging and load supply (H02J7/50 takes precedence) · CPC title

  • concerning the insertion or the connection of the batteries · CPC title

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What does patent US11081836B2 cover?
Methods and devices for wired charging and communication with a wearable device are described. In one embodiment, a symmetrical contact interface comprises a first contact pad and a second contact pad, and particular wired circuitry is coupled to the first and second contact pad to enable charging as well as receive and transmit communications via the contact pads as part of various device states.
Who is the assignee on this patent?
Snap Inc
What technology area does this patent fall under?
Primary CPC classification H02J7/68. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 03 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).