Semiconductor laminate, light-receiving element, and method for manufacturing semiconductor laminate

Patent metadata

Field	Value
Publication number	US-11081605-B2
Application number	US-201816635482-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Sep 1, 2017
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A semiconductor laminate includes a substrate formed of a group III-V compound semiconductor and a quantum well structure disposed on the substrate. The quantum well structure includes a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer. In the first element layer, the thickness of a region in which the content of Sb decreases in a direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.

First claim

The invention claimed is:

1. A semiconductor laminate comprising:
a substrate formed of a group III-V compound semiconductor; and
a quantum well structure disposed on the substrate,
wherein the quantum well structure includes
a second element layer formed of a group III-V compound semiconductor and containing Sb and
a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer,
wherein, in the first element layer, a thickness of a region in which a content of Sb decreases in a direction away from the substrate from 80% of a maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.

2. The semiconductor laminate according to claim 1 ,
wherein the quantum well structure is a type-II quantum well structure.

3. The semiconductor laminate according to claim 1 ,
wherein the first element layer is an In x Ga 1-x As (x is from 0.38 to 1 inclusive) layer or a Ga 1-u In u N v As 1-v (u is from 0.4 to 0.8 inclusive, and v is more than 0 and 0.2 or less) layer, and
wherein the second element layer is a GaAs 1-y Sb y (y is from 0.36 to 1 inclusive) layer.

4. The semiconductor laminate according to claim 1 ,
wherein, in the first element layer, the thickness of the region in which the content of Sb decreases in the direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 1.0 nm to 3.0 nm inclusive.

5. A semiconductor laminate comprising:
a substrate formed of a group III-V compound semiconductor; and
a quantum well structure disposed on the substrate,
wherein the quantum well structure includes
a second element layer formed of a group III-V compound semiconductor and containing Sb and
a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer,
wherein, in the first element layer, a thickness of a region in which a content of Sb decreases in a direction away from the substrate from 80% of a maximum content of Sb in the second element layer to 6% of the maximum content is from 1.0 nm to 3.0 nm inclusive,
wherein the quantum well structure is a type-II quantum well structure,
wherein the first element layer is an In x Ga 1-x As (x is from 0.38 to 1 inclusive) layer or a Ga 1-u In u N v As 1-v (u is from 0.4 to 0.8 inclusive, and v is more than 0 and 0.2 or less) layer, and
wherein the second element layer is a GaAs 1-y Sb y (y is from 0.36 to 1 inclusive) layer.

6. The semiconductor laminate according to claim 1 ,
wherein the substrate is formed of GaAs, GaP, GaSb, InP, InAs, InSb, AlSb, or AlAs.

7. A light-receiving device comprising:
the semiconductor laminate according to claim 1 ; and
electrodes formed on the semiconductor laminate.

8. A method for manufacturing a semiconductor laminate, the method comprising the steps of:
preparing a substrate formed of a group III-V compound semiconductor; and
forming epilayers formed of respective group III-V compound semiconductors on the substrate,
wherein the step of forming the epilayers includes the step of forming a quantum well structure,
wherein, in the step of forming the quantum well structure, a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer are formed, and
wherein, in the step of forming the quantum well structure, the first element layer and the second element layer are formed such that, in the first element layer, a thickness of a region in which a content of Sb decreases in a direction away from the substrate from 80% of a maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.

9. The method for manufacturing a semiconductor laminate according to claim 8 ,
wherein, in the step of forming the quantum well structure, the first element layer and the second element layer are formed such that, in the first element layer, the thickness of the region in which the content of Sb decreases in the direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 1.0 nm to 3.0 nm inclusive.

10. The method for manufacturing a semiconductor laminate according to claim 8 ,
wherein, in the step of forming the quantum well structure, the first element layer and the second element layer are formed in the temperature range of from 510° C. to 570° C. inclusive.

11. The method for manufacturing a semiconductor laminate according to claim 8 ,
wherein, in the step of forming the quantum well structure, the first element layer and the second element layer are formed under the condition that the ratio of the supply amount of a raw material of a group V element to the supply amount of a raw material of a group III element is 3 or less.

12. The method for manufacturing a semiconductor laminate according to claim 8 ,
wherein, in the step of forming the quantum well structure, the first element layer and the second element layer are formed at a growth rate of 0.1 μm/h or less.

Assignees

• Sumitomo Electric Industries

Inventors

• Fuyuki Takuma
• Doi Tomohiro
• Go Takashi
• Ishizuka Takashi

Classifications

• H10F77/1248

  having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP · CPC title

• H10F77/1243

  characterised by the dopants · CPC title

• H10F77/124

  comprising only Group III-V materials, e.g. GaAs · CPC title

• H10F71/1272

  comprising at least three elements, e.g. GaAlAs or InGaAsP · CPC title

• H10F30/222

  the potential barrier being a PN heterojunction · CPC title