Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses

Patent metadata

Field	Value
Publication number	US-11081468-B2
Application number	US-201916553549-A
Country	US
Kind code	B2
Filing date	Aug 28, 2019
Priority date	Aug 28, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
a first semiconductor die disposed proximate the substrate with an active surface facing an upper surface of the substrate and communicatively coupled to the substrate by direct chip attachment (DCA) interconnects; and
at least a second semiconductor die disposed over the first semiconductor die with a back side surface facing a back side surface of the first semiconductor die, wherein the at least the second semiconductor die is directly coupled to the substrate by first wire bonds
wherein the first semiconductor die is communicatively coupled to the second semiconductor die through the substrate.

2. The apparatus of claim 1 , wherein the at least a second semiconductor die comprises:
a third semiconductor die disposed over the at least the second semiconductor die with a back side surface facing an active surface of the at least the second semiconductor die, wherein the third semiconductor die is communicatively coupled to the at least the second semiconductor die by second wire bonds.

3. The apparatus of claim 1 , wherein the DCA interconnects are located between a center portion of the upper surface of the first semiconductor die and a center portion of the active surface of the substrate.

4. The apparatus of claim 3 , wherein first outer DCA interconnects are located along a first lateral end of the active surface of the first semiconductor die.

5. The apparatus of claim 4 , wherein second outer DCA interconnects are further located along a second opposite lateral end of the active surface of the first semiconductor die.

6. The apparatus of claim 1 , wherein the at least a second semiconductor die is directly coupled to the substrate by the first wire bonds, comprising:
a first set of wires coupled between a first lateral end of the upper surface of the substrate and a first lateral end of the active surface of the at least the second semiconductor die; and
a second set of wires coupled between the first lateral end of the upper surface of the substrate and the first lateral end of the active surface of the at least the second semiconductor die.

7. The apparatus of claim 6 , further comprising:
a third semiconductor die disposed over the at least the second semiconductor die, wherein the third semiconductor die is directly coupled to the at least the second semiconductor die by:
a third set of wires coupled between a first lateral end of the active surface of the third semiconductor die and the first lateral end of the active surface of the at least the second semiconductor die; and
a fourth set of wires coupled between a first lateral end of the active surface of the third semiconductor die and the first lateral end of the active surface of the at least the second semiconductor die.

8. The apparatus of claim 1 , wherein the at least the second semiconductor die is directly coupled to the substrate by the first wire bonds, comprising:
a first set of wires coupled between a first lateral end of the upper surface of the substrate and a first lateral end of the active surface of the at least the second semiconductor die; and
a second set of wires coupled between a second lateral end of the upper surface of the substrate and a second lateral end of the active surface of the at least the second semiconductor die.

9. The apparatus of claim 8 , further comprising:
a third semiconductor die disposed over the at least the second semiconductor die and directly coupled to the substrate by:
a third set of wires coupled between the first lateral end of the upper surface of the substrate and a first lateral end of an active surface of the third semiconductor die; and
a fourth set of wires coupled between the second lateral end of the upper surface of the substrate and a second lateral end of the active surface of the third semiconductor die.

10. The apparatus of claim 1 , wherein the first semiconductor die is a master die and the at least the second semiconductor die is a slave die.

11. The apparatus of claim 1 , wherein the first semiconductor die is configured to:
receive signals from the at least the second semiconductor die via the substrate; and
transmit the signals to the at least the second semiconductor die via the substrate.

12. A method of forming a stacked die device comprising:
disposing a first integrated circuit die over a substrate with an active surface of the first integrated circuit die facing an upper surface of the substrate;
electrically coupling the first integrated circuit die to the substrate via direct chip attachment (DCA) interconnects;
disposing a second integrated circuit die over the first integrated circuit die with a back side surface of the second integrated circuit die facing a back side surface of the first integrated circuit die; and
electrically coupling the second integrated circuit die directly to the substrate via first wire bonds;
wherein the first integrated circuit die is electrically coupled to the second integrated circuit die through the substrate.

13. The method of claim 12 , further comprising:
disposing a third integrated circuit die over the second integrated circuit die with a back side surface of the third integrated circuit die facing an active surface of the second integrated circuit die.

14. The method of claim 13 , further comprising:
electrically coupling the second integrated circuit die to the third integrated circuit die via second wire bonds.

15. The method of claim 14 , further comprising:
electrically coupling a first lateral end of the active surface of the second integrated circuit die to a first lateral end of an active surface of the third integrated circuit die via the second wire bonds.

16. The method of claim 13 , further comprising:
electrically coupling a first lateral end of an active surface of the third integrated circuit die to a first lateral end of the upper surface of the substrate via second wire bonds; and
electrically coupling a second, opposite, lateral end of the active surface of the third integrated circuit die to a second, opposite, lateral end of the upper surface of the substrate via the second wire bonds.

17. The method of claim 12 , further comprising:
electrically coupling a center portion of the active surface of the first integrated circuit die to a center portion of the upper surface of the substrate via the DCA interconnects.

18. The method of claim 17 , further comprising:
electrically coupling a first lateral end of the active surface of the first integrated circuit die to a first lateral end of the upper surface of the substrate via the DCA interconnects.

19. The method of claim 12 , further comprising:
electrically coupling a first lateral end of an active surface of the second integrated circuit die to a first lateral end of the upper surface of the substrate via the first wire bonds.

20. The method of claim 19 , further comprising:
electrically coupling a second lateral end of the active surface of the second integrated circuit die to a second lateral end of the upper surface of the substrate via the first wire bonds, wherein the second lateral end of the active surface of the second integrated circuit die is opposite the first lateral end of the active surface of the second integrated circuit die and the second lateral end of the upper surface of the substrate is opposite the first lateral end of the upper surface of the substrate.

21. A stacked die package, comprising:
a substrate;
a first

Assignees

• Micron Technology Inc

Inventors

• Fujisawa Hiroki
• Bansal Raj K
• Kuwahara Shunji
• Katagiri Mitsuaki
• Isa Satoshi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title